From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Christian_K=c3=b6nig?= Subject: Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6 Date: Wed, 17 Jan 2018 15:49:49 +0100 Message-ID: <2db2e630-2fe3-b3c7-8e7f-de7d4f67266d@amd.com> References: <20180116194017.39067-1-christian.koenig@amd.com> <20180116194017.39067-10-christian.koenig@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1821503242==" Return-path: In-Reply-To: Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Deucher, Alexander" , Alex Deucher Cc: amd-gfx list This is a multi-part message in MIME format. --===============1821503242== Content-Type: multipart/alternative; boundary="------------1E27C57CD4C4B0C750A93B51" Content-Language: en-US This is a multi-part message in MIME format. --------------1E27C57CD4C4B0C750A93B51 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Am 17.01.2018 um 15:22 schrieb Deucher, Alexander: > > > ------------------------------------------------------------------------ > *From:* amd-gfx on behalf of > Christian König > *Sent:* Wednesday, January 17, 2018 7:42 AM > *To:* Alex Deucher > *Cc:* amd-gfx list > *Subject:* Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6 > Am 16.01.2018 um 21:01 schrieb Alex Deucher: > > On Tue, Jan 16, 2018 at 2:40 PM, Christian König > > wrote: > >> Needed for vm_flush unification. > >> > >> Signed-off-by: Christian König > >> --- > >>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++ > >>   1 file changed, 12 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> index c6e22eff89e7..b48b843c66ae 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> @@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct > amdgpu_ring *ring, > >>          amdgpu_ring_write(ring, ib->length_dw); > >>   } > >> > >> +static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring, > >> +                                   uint32_t reg, uint32_t val) > >> +{ > >> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); > >> +       amdgpu_ring_write(ring, reg << 2); > >> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); > >> +       amdgpu_ring_write(ring, val); > >> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); > >> +       amdgpu_ring_write(ring, 0x8); > > Is this valid on UVD6? > > This is valid on the decode ring of UVD6, only the HEVC UVD6 encode and > VCE3 rings use different commands. > > >    I think this may be a UVD7 thing.  Looking at > > the other UVD code, I think we just want: > >          amdgpu_ring_write(ring, PACKET0(reg, 0)); > >          amdgpu_ring_write(ring, val); > > IIRC that won't work. The UVD RBC can only write to UVD registers using > the PACKET0 command. > > We probably need to fix a bunch of functions in uvd4,5,6,7 in that > case which use packet0 directly to write non-UVD registers. Yeah, I see. I briefly remember that I questioned if this works or not two years ago when we added the code. Going to wire things up correctly with the new wreg callback. Christian. > > Alex > > > Regards, > Christian. > > > > > Alex > > > > > >> +} > >> + > >>   static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, > >> unsigned vmid, unsigned pasid, > >> uint64_t pd_addr) > >> @@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs > uvd_v6_0_ring_vm_funcs = { > >>          .pad_ib = amdgpu_ring_generic_pad_ib, > >>          .begin_use = amdgpu_uvd_ring_begin_use, > >>          .end_use = amdgpu_uvd_ring_end_use, > >> +       .emit_wreg = uvd_v6_0_ring_emit_wreg, > >>   }; > >> > >>   static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = { > >> -- > >> 2.14.1 > >> > >> _______________________________________________ > >> amd-gfx mailing list > >> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx --------------1E27C57CD4C4B0C750A93B51 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: 8bit
Am 17.01.2018 um 15:22 schrieb Deucher, Alexander:


From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Christian König <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Wednesday, January 17, 2018 7:42 AM
To: Alex Deucher
Cc: amd-gfx list
Subject: Re: [PATCH 10/21] drm/amdgpu: wire up emit_wreg for UVD v6
 
Am 16.01.2018 um 21:01 schrieb Alex Deucher:
> On Tue, Jan 16, 2018 at 2:40 PM, Christian König
> <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> Needed for vm_flush unification.
>>
>> Signed-off-by: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> index c6e22eff89e7..b48b843c66ae 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> @@ -1059,6 +1059,17 @@ static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
>>          amdgpu_ring_write(ring, ib->length_dw);
>>   }
>>
>> +static void uvd_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
>> +                                   uint32_t reg, uint32_t val)
>> +{
>> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
>> +       amdgpu_ring_write(ring, reg << 2);
>> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
>> +       amdgpu_ring_write(ring, val);
>> +       amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
>> +       amdgpu_ring_write(ring, 0x8);
> Is this valid on UVD6?

This is valid on the decode ring of UVD6, only the HEVC UVD6 encode and
VCE3 rings use different commands.

>    I think this may be a UVD7 thing.  Looking at
> the other UVD code, I think we just want:
>          amdgpu_ring_write(ring, PACKET0(reg, 0));
>          amdgpu_ring_write(ring, val);

IIRC that won't work. The UVD RBC can only write to UVD registers using
the PACKET0 command.

We probably need to fix a bunch of functions in uvd4,5,6,7 in that case which use packet0 directly to write non-UVD registers.

Yeah, I see. I briefly remember that I questioned if this works or not two years ago when we added the code.

Going to wire things up correctly with the new wreg callback.

Christian.


Alex


Regards,
Christian.

>
> Alex
>
>
>> +}
>> +
>>   static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
>>                                          unsigned vmid, unsigned pasid,
>>                                          uint64_t pd_addr)
>> @@ -1595,6 +1606,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
>>          .pad_ib = amdgpu_ring_generic_pad_ib,
>>          .begin_use = amdgpu_uvd_ring_begin_use,
>>          .end_use = amdgpu_uvd_ring_end_use,
>> +       .emit_wreg = uvd_v6_0_ring_emit_wreg,
>>   };
>>
>>   static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = {
>> --
>> 2.14.1
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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