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[2001:4c4e:24ca:a400:8825:f46d:d14d:d33]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b723fa023adsm228522666b.51.2025.11.04.07.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Nov 2025 07:26:55 -0800 (PST) Message-ID: <30d7073e8289db8a2db9d1ae15b33ca50680364c.camel@gmail.com> Subject: Re: [PATCH 01/16] drm/amdgpu/gmc: Don't hardcode GART page count before GTT From: Timur =?ISO-8859-1?Q?Krist=F3f?= To: Pierre-Eric Pelloux-Prayer , Christian =?ISO-8859-1?Q?K=F6nig?= , amd-gfx@lists.freedesktop.org, Alex Deucher , Alexandre Demers , Rodrigo Siqueira , Leo Liu Date: Tue, 04 Nov 2025 16:26:54 +0100 In-Reply-To: <237b5110-bf9b-452a-ab51-51ca67f7589d@damsy.net> References: <20251103222333.37817-1-timur.kristof@gmail.com> <20251103222333.37817-2-timur.kristof@gmail.com> <9b4daf2b-d97d-4b3d-bd7b-3b136a4e304c@amd.com> <237b5110-bf9b-452a-ab51-51ca67f7589d@damsy.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) MIME-Version: 1.0 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Tue, 2025-11-04 at 16:08 +0100, Pierre-Eric Pelloux-Prayer wrote: >=20 >=20 > Le 04/11/2025 =C3=A0 14:23, Christian K=C3=B6nig a =C3=A9crit=C2=A0: > >=20 > >=20 > > On 11/3/25 23:23, Timur Krist=C3=B3f wrote: > > > GART contains some pages in its address space that come before > > > the GTT and are used for BO copies. > > >=20 > > > Instead of hardcoding the size of the GART space before GTT, > > > make it a field in the amdgpu_gmc struct. This allows us to map > > > more things in GART before GTT. > > >=20 > > > Split this into a separate patch to make it easier to bisect, > > > in case there are any errors in the future. > > >=20 > > > Signed-off-by: Timur Krist=C3=B3f > > > --- > > > =C2=A0 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c=C2=A0=C2=A0=C2=A0=C2= =A0 | 2 ++ > > > =C2=A0 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h=C2=A0=C2=A0=C2=A0=C2= =A0 | 1 + > > > =C2=A0 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 2 +- > > > =C2=A0 3 files changed, 4 insertions(+), 1 deletion(-) > > >=20 > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > > > index 97b562a79ea8..bf31bd022d6d 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > > > @@ -325,6 +325,8 @@ void amdgpu_gmc_gart_location(struct > > > amdgpu_device *adev, struct amdgpu_gmc *mc, > > > =C2=A0=C2=A0 break; > > > =C2=A0=C2=A0 } > > > =C2=A0=20 > > > + mc->num_gart_pages_before_gtt =3D > > > + AMDGPU_GTT_MAX_TRANSFER_SIZE * > > > AMDGPU_GTT_NUM_TRANSFER_WINDOWS; > > > =C2=A0=C2=A0 mc->gart_start &=3D ~(four_gb - 1); > > > =C2=A0=C2=A0 mc->gart_end =3D mc->gart_start + mc->gart_size - 1; > > > =C2=A0=C2=A0 dev_info(adev->dev, "GART: %lluM 0x%016llX - > > > 0x%016llX\n", > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h > > > index 55097ca10738..568eed3eb557 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h > > > @@ -266,6 +266,7 @@ struct amdgpu_gmc { > > > =C2=A0=C2=A0 u64 fb_end; > > > =C2=A0=C2=A0 unsigned vram_width; > > > =C2=A0=C2=A0 u64 real_vram_size; > > > + u32 num_gart_pages_before_gtt; > > > =C2=A0=C2=A0 int vram_mtrr; > > > =C2=A0=C2=A0 u64=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 mc_ma= sk; > > > =C2=A0=C2=A0 const struct firmware=C2=A0=C2=A0 *fw; /* MC firmware */ > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c > > > index 0760e70402ec..4c2563a70c2b 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c > > > @@ -283,7 +283,7 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device > > > *adev, uint64_t gtt_size) > > > =C2=A0=20 > > > =C2=A0=C2=A0 ttm_resource_manager_init(man, &adev->mman.bdev, > > > gtt_size); > > > =C2=A0=20 > > > - start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * > > > AMDGPU_GTT_NUM_TRANSFER_WINDOWS; > > > + start =3D adev->gmc.num_gart_pages_before_gtt; > >=20 > > I would prefer that we have a single function which returns the > > number of GART pages we need before the dynamic GTT mapping. > >=20 > > But let me see how Pierre-Eric solved this first. > >=20 >=20 > The only conflicting change with my series is that I changed this: >=20 > - start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * > AMDGPU_GTT_NUM_TRANSFER_WINDOWS; > + start =3D AMDGPU_GTT_MAX_TRANSFER_SIZE * reserved_windows; >=20 > So to account for Timur's change, I would only need to adapt this > part: >=20 > + mc->num_gart_pages_before_gtt =3D > + AMDGPU_GTT_MAX_TRANSFER_SIZE * reserved_windows; >=20 Hi Christian & Pierre-Eric, I assume this conversation is about the following series: drm/amdgpu: use all SDMA instances for TTM clears and moves My question is, which series do we want to land first? I would really like VCE1 to get into Linux 6.19, but otherwise I'm OK with either of these two options: 1. If Pierre-Eric's series lands sooner: I'm happy to rebase my work and use Pierre-Eric's solution. 2. If my series lands first: I'm happy to contribute a patch to Pierre- Eric's series to adapt my workaround to his solution, if that helps. Please let me know how you guys prefer to proceed. Thanks & best regards, Timur > >=20 > > > =C2=A0=C2=A0 size =3D (adev->gmc.gart_size >> PAGE_SHIFT) - start; > > > =C2=A0=C2=A0 drm_mm_init(&mgr->mm, start, size); > > > =C2=A0=C2=A0 spin_lock_init(&mgr->lock);