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Tue, 16 Nov 2021 08:56:48 +0000 Message-ID: <33df0fe4-95db-5663-eef0-0ad23b9cb149@amd.com> Date: Tue, 16 Nov 2021 14:26:36 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.3.0 Subject: Re: [PATCH] drm/amdgpu: support new mode-1 reset interface Content-Language: en-US To: "Zhou1, Tao" , "amd-gfx@lists.freedesktop.org" , "Zhang, Hawking" , "Clements, John" , "Yang, Stanley" , "Quan, Evan" References: <20211116072337.29600-1-tao.zhou1@amd.com> From: "Lazar, Lijo" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: PN3PR01CA0100.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:9b::22) To DM6PR12MB3930.namprd12.prod.outlook.com (2603:10b6:5:1c9::19) MIME-Version: 1.0 Received: from [10.252.81.250] (165.204.159.242) by PN3PR01CA0100.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:9b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4690.16 via Frontend Transport; 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I assume the PMFW of new smu v13 ASIC in the future will follow this design, otherwise we could move the implementation into xxx_ppt.c. > Actually, this is meant to be a common logic for SMU13 based ASICs. The version check in a common file is not maintainable. I see there is a version check before also, even that is not proper :) It is better to do it properly when support is added rather than thinking of refactoring with future ASICs. Thanks, Lijo > Regards, > Tao > >> -----Original Message----- >> From: Lazar, Lijo >> Sent: Tuesday, November 16, 2021 3:44 PM >> To: Zhou1, Tao ; amd-gfx@lists.freedesktop.org; Zhang, >> Hawking ; Clements, John >> ; Yang, Stanley ; Quan, >> Evan >> Subject: Re: [PATCH] drm/amdgpu: support new mode-1 reset interface >> >> >> >> On 11/16/2021 12:53 PM, Tao Zhou wrote: >>> If gpu reset is triggered by ras fatal error, tell it to smu in mode-1 >>> reset message. >>> >>> Signed-off-by: Tao Zhou >>> --- >>> .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 21 >> ++++++++++++++++--- >>> 1 file changed, 18 insertions(+), 3 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c >>> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c >>> index 35145db6eedf..6f3d064a8232 100644 >>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c >>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c >>> @@ -1426,16 +1426,31 @@ int smu_v13_0_set_azalia_d3_pme(struct >>> smu_context *smu) >>> >>> int smu_v13_0_mode1_reset(struct smu_context *smu) >>> { >>> - u32 smu_version; >>> + u32 smu_version, fatal_err, param; >>> int ret = 0; >>> + struct amdgpu_device *adev = smu->adev; >>> + struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); >>> + >>> + fatal_err = 0; >>> + param = SMU_RESET_MODE_1; >>> + >>> /* >>> * PM FW support SMU_MSG_GfxDeviceDriverReset from 68.07 >>> */ >>> smu_cmn_get_smc_version(smu, NULL, &smu_version); >>> if (smu_version < 0x00440700) >>> ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, >> NULL); >>> - else >>> - ret = smu_cmn_send_smc_msg_with_param(smu, >> SMU_MSG_GfxDeviceDriverReset, SMU_RESET_MODE_1, NULL); >>> + else { >>> + /* fatal error triggered by ras, PMFW supports the flag >>> + from 68.44.0 */ >>> + if ((smu_version >= 0x00442c00) && ras && >>> + atomic_read(&ras->in_recovery)) >>> + fatal_err = 1; >>> + >> >> From PMFW version, this looks specific to aldebaran. Since there is version >> check as well, the implementation needs to be moved to aldebaran_ppt.c >> >> Thanks, >> Lijo >> >>> + param |= (fatal_err << 16); >>> + ret = smu_cmn_send_smc_msg_with_param(smu, >>> + SMU_MSG_GfxDeviceDriverReset, >> param, NULL); >>> + } >>> >>> if (!ret) >>> msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS); >>>