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[84.1.223.139]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e13235f5sm12617367f8f.29.2026.01.29.01.41.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 01:41:56 -0800 (PST) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org Cc: Alex Deucher , Alex Deucher Subject: Re: [PATCH 1/3] drm/amdgpu/gfx10: fix wptr reset in KGQ init Date: Thu, 29 Jan 2026 10:41:55 +0100 Message-ID: <3572729.LZWGnKmheA@timur-hyperion> In-Reply-To: <20260129043446.33377-1-alexander.deucher@amd.com> References: <20260129043446.33377-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Thursday, January 29, 2026 5:34:44=E2=80=AFAM Central European Standard = Time Alex=20 Deucher wrote: > wptr is a 64 bit value and we need to update the > full value, not just 32 bits. Align with what we > already do for KCQs. >=20 > Signed-off-by: Alex Deucher Reviewed-by: Timur Krist=C3=B3f for the series. I notice that the code base already does this for gfx9, but is rather=20 inconsistent on gfx6-8. If you think that's useful, I could submit some=20 patches to do the same on older GPUs. What do you think? > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index e9254ec3b6417..ef7d91a4437= ec > 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -6883,7 +6883,7 @@ static int gfx_v10_0_kgq_init_queue(struct amdgpu_r= ing > *ring, bool reset) memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], > sizeof(*mqd)); /* reset the ring */ > ring->wptr =3D 0; > - *ring->wptr_cpu_addr =3D 0; > + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); > amdgpu_ring_clear_ring(ring); > }