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[176.77.154.214]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48a822bf3ffsm71712115e9.7.2026.04.30.06.19.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2026 06:19:38 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, alexander.deucher@amd.com, Alex Hung , Harry Wentland , Roman Li , Leo Li , David Airlie , Mario Limonciello , Ivan Lipski , Melissa Wen Subject: Re: [PATCH 05/14] drm/amd/display: Set max supported display clock without max_clks_by_state Date: Thu, 30 Apr 2026 14:28:27 +0200 Message-ID: <3591364.LZWGnKmheA@timur-max> In-Reply-To: References: <20260423191519.73127-1-timur.kristof@gmail.com> <20260423191519.73127-6-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. =C3=A1prilis 29., szerda 22:24:38 k=C3=B6z=C3=A9p-eur=C3=B3pai ny= =C3=A1ri id=C5=91 Melissa Wen=20 wrote: > On 23/04/2026 16:15, Timur Krist=C3=B3f wrote: > > The max_clks_by_state was based on hardcoded values, which are > > not really used anywhere, only to know the maximum clock. > > Just hardcode the same maximum clock for each DCE version. > >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > .../amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 16 +++++++++++----- > > 1 file changed, 11 insertions(+), 5 deletions(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c > > b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c index > > 2ba341df7fffd..bef9a72f3382f 100644 > > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c > > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c > > @@ -391,9 +391,7 @@ static void dce_update_clocks(struct clk_mgr > > *clk_mgr_base,>=20 > > struct dc_state *context, > > bool safe_to_lower) > > =20 > > { > >=20 > > - struct clk_mgr_internal *clk_mgr_dce =3D > > TO_CLK_MGR_INTERNAL(clk_mgr_base); > > - const int max_disp_clk =3D > > - clk_mgr_dce- >max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_ > > clk_khz; + const int max_disp_clk =3D > > clk_mgr_base->clks.max_supported_dispclk_khz;>=20 > > int patched_disp_clk =3D MIN(max_disp_clk, > > context->bw_ctx.bw.dce.dispclk_khz); > > =09 > > if (should_set_clock(safe_to_lower, patched_disp_clk, > > clk_mgr_base->clks.dispclk_khz)) {>=20 > > @@ -445,8 +443,16 @@ void dce_clk_mgr_construct( > >=20 > > clk_mgr->dprefclk_ss_divider =3D 1000; > > clk_mgr->ss_on_dprefclk =3D false; > >=20 > > - base->clks.max_supported_dispclk_khz =3D > > - clk_mgr- >max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_ > > khz; + if (ctx->dce_version >=3D DCE_VERSION_12_0) > > + base->clks.max_supported_dispclk_khz =3D 1133000; > > + else if (ctx->dce_version >=3D DCE_VERSION_11_2) > > + base->clks.max_supported_dispclk_khz =3D 1108000; >=20 > For DCE 11.2, I see ClocksStatePerformance is 1132000 instead of > 1108000, right? Hi Melissa, =46or DCE11.2, nobody really knows what the maximum supported display clock= is. There are different values hardcoded in different parts of the code base. dce112_max_clks_by_state says it's 1132 MHz bw_calcs says it's 1108 MHz and dce112_update_clocks() adds 15% In this patch, I chose to go for 1108 MHz to match bw_calcs, but I can edit= =20 that if you feel that 1132 MHz is better. What do you think? Thanks, Timur >=20 > With the value fixed, this is: >=20 > Reviewed-by: Melissa Wen >=20 > > + else if (ctx->dce_version >=3D DCE_VERSION_11_0) > > + base->clks.max_supported_dispclk_khz =3D 643000; > > + else if (ctx->dce_version >=3D DCE_VERSION_8_0) > > + base->clks.max_supported_dispclk_khz =3D 625000; > > + else > > + base->clks.max_supported_dispclk_khz =3D 600000; > >=20 > > dce_clock_read_integrated_info(clk_mgr); > > dce_clock_read_ss_info(clk_mgr);