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[84.1.223.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-679b6843509sm565723a12.18.2026.04.28.03.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2026 03:20:47 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org Cc: Alex Deucher , Alex Deucher Subject: Re: [PATCH 1/2] drm/amdgpu/pm: add missing revision check for CI Date: Tue, 28 Apr 2026 12:20:46 +0200 Message-ID: <3692901.dWV9SEqChM@timur-hyperion> In-Reply-To: <20260427173103.1020723-1-alexander.deucher@amd.com> References: <20260427173103.1020723-1-alexander.deucher@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Hi Alex, On Monday, April 27, 2026 7:31:02=E2=80=AFPM Central European Summer Time A= lex Deucher=20 wrote: > The ci_populate_all_memory_levels() workaround only > applies to revision 0 SKUs. This makes good sense. Looking at issue 1816, seems that the affected GPU i= s=20 revision 80, and looking at my Hawaii card, it seems to be also 80: 01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ ATI] Hawaii XT / Grenada XT [Radeon R9 290X/390X] [1002:67b0] (rev 80) (pro= g- if 00 [VGA controller]) Can you please add a few tags for additional context? Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/1816 =46ixes: 9f4b35411cfe ("drm/amd/powerplay: add CI asics support to smumgr (= v3)") >=20 > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c > b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c index > 69d8b05ef2457..6e89a032e3dcf 100644 > --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c > +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c > @@ -1333,8 +1333,9 @@ static int ci_populate_all_memory_levels(struct > pp_hwmgr *hwmgr) >=20 > dev_id =3D adev->pdev->device; >=20 > - if ((dpm_table->mclk_table.count >=3D 2) > - && ((dev_id =3D=3D 0x67B0) || (dev_id =3D=3D 0x67B1))) { > + if ((dpm_table->mclk_table.count >=3D 2) && > + ((dev_id =3D=3D 0x67B0) || (dev_id =3D=3D 0x67B1)) && > + (adev->pdev->revision =3D=3D 0)) { > smu_data->smc_state_table.MemoryLevel[1].MinVddci =3D > smu_data- >smc_state_table.MemoryLevel[0].MinVddci; > smu_data->smc_state_table.MemoryLevel[1].MinMvdd =3D It looks like amdgpu and radeon behave differently here: radeon overwrites = the=20 MinVddc and MinVddcPhases vs. amdgpu overwrites MinVddci and MinMvdd. Without knowing more details of what the workaround was trying to achieve,= =20 it's hard to judge whether radeon or amdgpu was correct, but it would be ni= ce=20 to make them consistent. If radeon was correct, could you adjust the amdgpu= =20 code here to do the same? (Or vice versa if amdgpu was correct.) With that, the series is: Reviewed-by: Timur Krist=C3=B3f Thanks & best regards, Timur