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[165.204.72.6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e73e85ccsm9379024f8f.42.2024.09.17.05.21.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Sep 2024 05:21:09 -0700 (PDT) Message-ID: <38063fdb-03d1-4b44-9835-105f756a0ed0@gmail.com> Date: Tue, 17 Sep 2024 14:21:07 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v11 26/28] drm/amdgpu: fix MES GFX mask To: Shashank Sharma , amd-gfx@lists.freedesktop.org Cc: Arvind Yadav , =?UTF-8?Q?Christian_K=C3=B6nig?= , Alex Deucher References: <20240909200614.481-1-shashank.sharma@amd.com> <20240909200614.481-22-shashank.sharma@amd.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20240909200614.481-22-shashank.sharma@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 09.09.24 um 22:06 schrieb Shashank Sharma: > From: Arvind Yadav > > Current MES GFX mask prevents FW to enable oversubscription. This patch > does the following: > - Fixes the mask values and adds a description for the same > - Removes the central mask setup and makes it IP specific, as it would > be different when the number of pipes and queues are different. > > Cc: Christian König > Cc: Alex Deucher > Signed-off-by: Shashank Sharma > Signed-off-by: Arvind Yadav > Change-Id: I86f5b89c5527c23df94edc707c69c78819f4c8cf Acked-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 --- > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 +- > drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 9 +++++++-- > 3 files changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > index f7d5d4f08a53..dbf19122dfc3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > @@ -151,9 +151,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) > adev->mes.compute_hqd_mask[i] = 0xc; > } > > - for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) > - adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe; > - > for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) { > if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < > IP_VERSION(6, 0, 0)) > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h > index 96788c0f42f1..45e3508f0f8e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h > @@ -109,8 +109,8 @@ struct amdgpu_mes { > > uint32_t vmid_mask_gfxhub; > uint32_t vmid_mask_mmhub; > - uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; > uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; > + uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; > uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; > uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; > uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > index 2911c45cfbe0..d2610a664b2a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > @@ -653,8 +653,13 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) > mes_set_hw_res_pkt.compute_hqd_mask[i] = > mes->compute_hqd_mask[i]; > > - for (i = 0; i < MAX_GFX_PIPES; i++) > - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; > + /* > + * GFX pipe 0 queue 0 is being used by kernel > + * Set GFX pipe 0 queue 1 for MES scheduling > + * GFX pipe 1 can't be used for MES due to HW limitation. > + */ > + mes_set_hw_res_pkt.gfx_hqd_mask[0] = 0x2; > + mes_set_hw_res_pkt.gfx_hqd_mask[1] = 0; > > for (i = 0; i < MAX_SDMA_PIPES; i++) > mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];