On 10-Sep-26 11:43 AM, SRINIVASAN SHANMUGAM wrote:
On 9/10/2026 2:20 AM, Alex Deucher wrote:
On Wed, Sep 9, 2026 at 4:42 PM Alex Deucher<alexdeucher@gmail.com> wrote:
On Sat, Sep 5, 2026 at 4:55 AM Srinivasan ShanmugamI would merge these patch sets. The trap handling is the same for
<srinivasan.shanmugam@amd.com> wrote:
MES owns kernel queue VMIDs (1..first_kfd_vmid-1) but does not programThese should be the same for both user and kernel queues. The only
SQ_SHADER_TBA/TMA for them. On GFX11+ hardware MES maps kernel queues
via ADD_QUEUE with map_legacy_kq=1 but does not set trap handler state.
On GFX10 and earlier HWS-based hardware, the driver programs trap
registers via SRBM select for KFD queues but no equivalent exists for
driver-managed kernel queue VMIDs.
Add a vmhub callback program_kernel_trap_vmids() so each gfxhub version
can write SQ_SHADER_TBA/TMA for kernel VMIDs. The TBA points to the
device-level CWSR ISA BO. The TMA is set to the fixed per-VM virtual
address AMDGPU_VA_RESERVED_TRAP_START — each VM maps its own kq_tma_bo
there, so per-VM isolation is handled entirely by page tables without
needing to reprogram the register per job or per submission.
The per-VM kq_tma_bo is a small GTT BO allocated at VM creation time
(parallel to page table allocation) and mapped read-only into the GPU VM
at AMDGPU_VA_RESERVED_TRAP_START. The kernel CPU writes the second-level
handler address into it via kq_tma_map when userspace calls SET_L2_TRAP.
The first-level CWSR handler reads this address to chain to the
second-level handler when a shader exception fires.
This design is:
- Per-VM BO (not device-level) — same model as page tables
- Fixed VA in each VM's address space — same VA, different physical BO
- Read-only from GPU — kernel CPU updates it via CPU mapping
- Treat allocation/free lifecycle identical to page tables
Suggested-by: Christian König<christian.koenig@amd.com>
Suggested-by: Alexander Deucher<alexander.deucher@amd.com>
Cc: Lijo Lazar<lijo.lazar@amd.com>
Cc: Timur Kristóf<timur.kristof@gmail.com>
Cc: Samuel Pitoiset<hakzsam@gmail.com>
Cc: Natalie Vock<natalie.vock@gmx.de>
Signed-off-by: Srinivasan Shanmugam<srinivasan.shanmugam@amd.com>
Change-Id: I9ce352157c4aa84099cef926cba61264781e8ad9
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_trap.c | 80 ++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_trap.h | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 9 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 13 ++++
5 files changed, 110 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 3ca187f5ade8..5624a5ab5c62 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -115,6 +115,7 @@ struct amdgpu_vmhub_funcs {
void (*print_l2_protection_fault_status)(struct amdgpu_device *adev,
uint32_t status);
uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type);
+ void (*program_kernel_trap_vmids)(struct amdgpu_device *adev);
};
struct amdgpu_vmhub {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trap.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_trap.c
index 623cac6781be..e913488ca3fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trap.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trap.c
@@ -263,6 +263,7 @@ int amdgpu_trap_init(struct amdgpu_device *adev)
amdgpu_trap_cwsr_init_save_area_info(adev, trap_info);
adev->trap_info = no_free_ptr(trap_info);
+ amdgpu_trap_program_kernel_vmids(adev);
return 0;
}
@@ -277,6 +278,85 @@ void amdgpu_trap_fini(struct amdgpu_device *adev)
adev->trap_info = NULL;
}
+void amdgpu_trap_program_kernel_vmids(struct amdgpu_device *adev)
+{
+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
+
+ if (!amdgpu_trap_is_enabled(adev))
+ return;
+ if (!hub->vmhub_funcs || !hub->vmhub_funcs->program_kernel_trap_vmids)
+ return;
+
+ hub->vmhub_funcs->program_kernel_trap_vmids(adev);
+}
+
+int amdgpu_trap_vm_kq_tma_alloc(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm)
+{
+ void *cpu_addr;
+ uint64_t va;
+ int r;
+
+ dma_resv_assert_held(vm->root.bo->tbo.base.resv);
+
+ r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT, &vm->kq_tma_bo,
+ NULL, &cpu_addr);
+ if (r)
+ return r;
+
+ if (vm->kq_tma_bo->kmap.bo_kmap_type & TTM_BO_MAP_IOMEM_MASK)
+ iosys_map_set_vaddr_iomem(&vm->kq_tma_map,
+ (void __iomem *)cpu_addr);
+ else
+ iosys_map_set_vaddr(&vm->kq_tma_map, cpu_addr);
+
+ vm->kq_tma_va = amdgpu_vm_bo_add(adev, vm, vm->kq_tma_bo);
+ if (!vm->kq_tma_va) {
+ r = -ENOMEM;
+ goto err_free_bo;
+ }
+
+ va = AMDGPU_VA_RESERVED_TRAP_START(adev) & AMDGPU_GMC_HOLE_MASK;
+ r = amdgpu_vm_bo_map(adev, vm->kq_tma_va, va, 0,
+ AMDGPU_GPU_PAGE_SIZE,
+ AMDGPU_VM_PAGE_READABLE);
+ if (r)
+ goto err_del_va;
+
+ r = amdgpu_vm_bo_update(adev, vm->kq_tma_va, false);
+ if (r)
+ goto err_del_va;
+
+ return 0;
+
+err_del_va:
+ amdgpu_vm_bo_del(adev, vm->kq_tma_va);
+ vm->kq_tma_va = NULL;
+err_free_bo:
+ amdgpu_bo_free_kernel(&vm->kq_tma_bo, NULL, NULL);
+ return r;
+}
+
+void amdgpu_trap_vm_kq_tma_free(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm)
+{
+ uint64_t va;
+
+ if (!vm->kq_tma_bo)
+ return;
+
+ dma_resv_assert_held(vm->root.bo->tbo.base.resv);
+
+ if (vm->kq_tma_va) {
+ va = AMDGPU_VA_RESERVED_TRAP_START(adev) & AMDGPU_GMC_HOLE_MASK;
+ amdgpu_vm_bo_unmap(adev, vm->kq_tma_va, va);
+ amdgpu_vm_bo_del(adev, vm->kq_tma_va);
+ vm->kq_tma_va = NULL;
+ }
+ amdgpu_bo_free_kernel(&vm->kq_tma_bo, NULL, NULL);
+}
+
static int amdgpu_trap_map_region(struct amdgpu_device *adev,
struct amdgpu_vm *vm,
struct amdgpu_trap_obj *cwsr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trap.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trap.h
index 7f83174a4742..9be5035abd1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trap.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trap.h
@@ -155,4 +155,11 @@ int amdgpu_trap_set_trap_debug_flag(struct amdgpu_device *adev,
struct amdgpu_trap_obj *cwsr_obj,
bool enabled);
+/* Kernel queue trap handler — per-VM TMA and register programming */
+void amdgpu_trap_program_kernel_vmids(struct amdgpu_device *adev);
+int amdgpu_trap_vm_kq_tma_alloc(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm);
+void amdgpu_trap_vm_kq_tma_free(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm);
+
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index de3ef9ce2234..f5e228d4bfb5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2640,6 +2640,12 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
if (r)
goto error_free_root;
+ if (amdgpu_trap_is_enabled(adev)) {
+ r = amdgpu_trap_vm_kq_tma_alloc(adev, vm);
+ if (r)
+ goto error_free_root;
+ }
+
r = amdgpu_vm_create_task_info(vm);
if (r)
dev_dbg(adev->dev, "Failed to create task info for VM\n");
@@ -2774,6 +2780,9 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
}
+ if (vm->kq_tma_bo)
+ amdgpu_trap_vm_kq_tma_free(adev, vm);
+
amdgpu_vm_pt_free_root(adev, vm);
amdgpu_bo_unreserve(root);
amdgpu_bo_unref(&root);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index dd825e179979..064f95a83790 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -25,6 +25,7 @@
#define __AMDGPU_VM_H__
#include <linux/idr.h>
+#include <linux/iosys-map.h>
#include <linux/kfifo.h>
#include <linux/rbtree.h>
#include <drm/gpu_scheduler.h>
@@ -488,6 +489,18 @@ struct amdgpu_vm {
/* cached fault info */
struct amdgpu_vm_fault_info fault_info;
+
+ /*
+ * Per-VM kernel queue first-level TMA BO.
+ * Allocated at VM init, freed at VM fini — same lifecycle as page tables.
+ * Mapped read-only at AMDGPU_VA_RESERVED_TRAP_START in the GPU VM.
+ * SQ_SHADER_TMA for all kernel VMIDs points to this fixed VA; per-VM
+ * isolation is via page tables mapping different physical BOs there.
+ * CPU kernel writes second-level handler address via kq_tma_map.
+ */
+ struct amdgpu_bo *kq_tma_bo;
+ struct amdgpu_bo_va *kq_tma_va;
+ struct iosys_map kq_tma_map;
difference is who manages the vmids (driver vs MES). They are per
vmid so it doesn't matter whether it's a kernel queue or user queue.
both kernel queues and user queues. The only difference for kernel
queues is that the driver has to set the TBA/TMA registers while
MES/KIQ handles it for user queues. At vm_init time, allocate the
memory for the trap handler, copy the trap handler to the memory and
add the mapping to the GPUVM address space. Then in gfxhub init,
program the TBA/TMA registers for the kernel managed vmids. Finally,
add the IOCTL to set/clear the second level trap handler and validate
the user supplied GPU VA.
Hi Alex,
Thank you for the review. I have few questions before proceeding with the implementation.
I looked at how KFD handles this today in |kfd_process.c|:
/* KFD writes second-level TBA/TMA into first-level TMA */
iosys_map_wr(&qpd->cwsr_map, KFD_CWSR_TMA_OFFSET,
uint64_t, tba_addr);
iosys_map_wr(&qpd->cwsr_map, KFD_CWSR_TMA_OFFSET + sizeof(uint64_t),
uint64_t, tma_addr);
Where |KFD_CWSR_TMA_OFFSET = AMDGPU_GPU_PAGE_SIZE + 2048 = 0x1800|. KFD uses physical GPU addresses for TBA/TMA registers, not VM virtual addresses.
KFD doesn't use physical adddress, it uses the below fixed virtual address.
pdd->qpd.cwsr_base = AMDGPU_VA_RESERVED_TRAP_START(pdd->dev->adev)
KFD mechanism is to allocate one BO which is mapped to the above virtual address. That BO accounts for both TMA and TBA size. TMA is located at KFD_CWSR_TMA_OFFSET within that BO.
TBA region carries the first level handler code. It's not allowed to be overridden by user. Hence when we moved to new design, TBA is kept common for all user VMs.
TMA BO is the place through where user's second level TMA/TBA addresses are passed and also the place where stack is saved.
iosys_map_wr(&qpd->cwsr_map, KFD_CWSR_TMA_OFFSET,
uint64_t, tba_addr);
iosys_map_wr(&qpd->cwsr_map, KFD_CWSR_TMA_OFFSET + sizeof(uint64_t),
uint64_t, tma_addr);
What this code does is to write the second level handler tba/tma addresses in the TMA, which is located at KFD_CWSR_TMA_OFFSET within the BO.
TMA region is the only variable thing per VM. First level handler code executed is the same for all VMs. So in the new design, we have a first level TBA BO that is shared by all VMs, and that carries first level trap handler code. The second level TBA is allocated per VM.
I see Alex is saying the same thing which I asked through a different thread. There is no need to allocate separate BOs for kernel queues. All you need to do is program the fixed TBA/TMA first level virtual addresses for non-KFD VMs during init.
Regarding kernel queue draining - my understanding is that the condition is no work having that VMID is in progress during the change. So, it may not be required to entirely drain kernel queue.
Thanks,
Lijo
I would like to take a moment to summarize what has been agreed upon and share my thoughts on the remaining open points, to ensure we are all aligned.
What is agreed:
AMDGPU_VA_RESERVED_TRAP_START — same
as KFD0x1800 from BO start —
matching KFD_CWSR_TMA_OFFSETSQ_SHADER_TBA/TMA registers programmed in gfxhub
init — kernel VMIDs onlykq_tba_bo/kq_tma_boSET_L2_TRAP: evict user queues, ensure no VMID
work in progress, write TMA, flush TLOpen Point 1 — Shared TBA or per-VM TBA copy?
Alex said: "copy the trap handler to the memory at
vm_init" → sounds like per-VM copy.
Lijo said: "TBA is kept common for all user VMs" →
sounds like one shared BO.
IMO: The first-level handler code (ISA binary) is
identical across all VMs for the same hardware. Based on this, one
option is to keep a single shared device-level TBA BO (adev->trap_info->isa_bo)
mapped into each VM at AMDGPU_VA_RESERVED_TRAP_START,
and allocate only the TMA BO per-VM at vm_init. This
avoids duplicating the same ISA binary N times in memory. Please
let me know if a per-VM TBA copy is preferred instead.
Open Point 2 — What happens to AMDGPU_VA_RESERVED_TRAP_UQ_START?
After merging, AMDGPU_VA_RESERVED_TRAP_START
covers both UQ and KQ in one buffer.
IMO: Remove AMDGPU_VA_RESERVED_TRAP_UQ_START
from the reserved VA space entirely since it is no longer needed.
Open Point 3 — When to set TRAP_EN?
IMO: Set TRAP_EN at
gfxhub init time. Since the per-VM TMA BO is always allocated at vm_init
before any work is submitted, AMDGPU_VA_RESERVED_TRAP_START
is always valid when any shader executes. No need to defer.
Open Point 4 — How to ensure no VMID work is in progress?
WhenSET_L2_TRAP is called, the TMA slots must be
written only when no GPU work is actively executing under that VMID.
One option is to use amdgpu_vm_wait_idle() before
writing the TMA slots, which waits for all pending GPU work in the
VM to complete. This is already used in the existing trap handler
code for the same purpose. Please confirm if this is sufficient or
if a different mechanism is needed.
Please confirm or correct any of the above
I would greatly appreciate it if anyone has a different perspective on any of the above or anything missing to be included or added — so that the design is aligned with everyone.
Regards,
Srini
Question 1 — Which fixed GPU virtual address for the merged buffer?
KFD uses physical addresses for the TBA/TMA registers. Our design maps the buffer into each VM at a fixed virtual address for page table isolation. Should the merged per-VM buffer use | AMDGPU_VA_RESERVED_TRAP_UQ_START| as the fixed VA? Or a different address?
Question 2 — TMA offset inside the merged buffer — 0x1800 or 0x2000?
KFD places the TMA section at offset |0x1800| from the TBA start (| KFD_CWSR_TMA_OFFSET|). The current UQ design uses offset |0x2000| (| AMDGPU_TRAP_TBA_MAX_SIZE|). After merging into one per-VM buffer, should TMA start at |0x1800| to match KFD's layout?
Question 3 — When should TRAP_EN be set?
When programming |SQ_SHADER_TBA_HI| for kernel VMIDs, should |TRAP_EN| be set only after the per-VM buffer is fully mapped? Or is it safe to set it at boot time since TMA slots start zeroed (meaning no second- level handler installed yet)?
Question 4 — Drain kernel queues before writing second-level handler?
When |SET_L2_TRAP| is called, user queues are evicted and TLB is flushed before writing. After the merge, kernel queue VMIDs also read from the same TMA. Should kernel queue work be drained as well before writing the second-level handler addresses?
Thanks,
Srini