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([2a02:908:1256:79a0:e2f8:820b:7a40:97ca]) by smtp.gmail.com with ESMTPSA id h13-20020a1709070b0d00b0094efdfe60dcsm780541ejl.206.2023.05.05.04.13.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 May 2023 04:13:41 -0700 (PDT) Message-ID: <412dddbe-67a1-48c4-1eb5-9cb7d672d79e@gmail.com> Date: Fri, 5 May 2023 13:13:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH] drm/amdgpu: avoid null dereference of fence when using cpu to update page tables Content-Language: en-US To: Lang Yu , amd-gfx@lists.freedesktop.org References: <20230505091020.1383923-1-Lang.Yu@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= In-Reply-To: <20230505091020.1383923-1-Lang.Yu@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jack Xiao , Christian Koenig Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 05.05.23 um 11:10 schrieb Lang Yu: > Using cpu to update page tables is sychronous, no need to wait fence > and it is NULL in such a case. Good catch, be we usually install the stub into fence pointers when they are unused. See dma_fence_get_stub(). Christian. > > Signed-off-by: Lang Yu > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > index f0f00466b59f..197981c4ac7d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > @@ -1043,8 +1043,11 @@ int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, > > amdgpu_mes_ring_to_queue_props(adev, ring, &qprops); > > - dma_fence_wait(gang->process->vm->last_update, false); > - dma_fence_wait(ctx_data->meta_data_va->last_pt_update, false); > + if (gang->process->vm->last_update) > + dma_fence_wait(gang->process->vm->last_update, false); > + if (ctx_data->meta_data_va->last_pt_update) > + dma_fence_wait(ctx_data->meta_data_va->last_pt_update, false); > + > amdgpu_mes_unlock(&adev->mes); > > r = amdgpu_mes_add_hw_queue(adev, gang_id, &qprops, &queue_id);