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Fri, 30 Jan 2026 15:05:16 +0000 Message-ID: <42191bbf-6f92-4883-8aa9-9e808fae3e8d@amd.com> Date: Fri, 30 Jan 2026 20:35:10 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions To: Alex Deucher Cc: Alex Deucher , amd-gfx@lists.freedesktop.org, Yifan Zhang References: <20260126200747.13527-1-alexander.deucher@amd.com> Content-Language: en-US From: "Lazar, Lijo" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: PN3PR01CA0144.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:bf::11) To SA0PR12MB7091.namprd12.prod.outlook.com (2603:10b6:806:2d5::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA0PR12MB7091:EE_|LV0PR12MB999091:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d05dd21-9f7a-4a91-abaf-08de6010f9c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016; 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The fix probably should be in the higher level sequence which >> doesn't take care of that. > > In that case, Yifan's original patch is probably fine as is. Someone > should still double check all of the call paths though. > Original one is also not correct. For example, if this is happening after reset re initialization, only that sequence needs to be modified to keep the affected IPs ungated during reinit. Thanks, Lijo > Alex > >> >> Thanks, >> Lijo >> >>> Cc: Yifan Zhang >>> Signed-off-by: Alex Deucher >>> --- >>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++++ >>> 1 file changed, 10 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >>> index 36f0300a21bfa..05178ee8e0e3a 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >>> @@ -6056,6 +6056,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, >>> u32 cp_int_cntl_reg, cp_int_cntl; >>> int i, j; >>> >>> + amdgpu_gfx_off_ctrl(adev, false); >>> switch (state) { >>> case AMDGPU_IRQ_STATE_DISABLE: >>> case AMDGPU_IRQ_STATE_ENABLE: >>> @@ -6080,6 +6081,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev, >>> default: >>> break; >>> } >>> + amdgpu_gfx_off_ctrl(adev, true); >>> >>> return 0; >>> } >>> @@ -6092,6 +6094,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev, >>> u32 cp_int_cntl_reg, cp_int_cntl; >>> int i, j; >>> >>> + amdgpu_gfx_off_ctrl(adev, false); >>> switch (state) { >>> case AMDGPU_IRQ_STATE_DISABLE: >>> case AMDGPU_IRQ_STATE_ENABLE: >>> @@ -6116,6 +6119,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev, >>> default: >>> break; >>> } >>> + amdgpu_gfx_off_ctrl(adev, true); >>> >>> return 0; >>> } >>> @@ -6125,6 +6129,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, >>> unsigned type, >>> enum amdgpu_interrupt_state state) >>> { >>> + amdgpu_gfx_off_ctrl(adev, false); >>> switch (state) { >>> case AMDGPU_IRQ_STATE_DISABLE: >>> case AMDGPU_IRQ_STATE_ENABLE: >>> @@ -6135,6 +6140,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev, >>> default: >>> break; >>> } >>> + amdgpu_gfx_off_ctrl(adev, true); >>> >>> return 0; >>> } >>> @@ -6152,6 +6158,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, >>> unsigned type, >>> enum amdgpu_interrupt_state state) >>> { >>> + amdgpu_gfx_off_ctrl(adev, false); >>> switch (state) { >>> case AMDGPU_IRQ_STATE_DISABLE: >>> WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, >>> @@ -6173,6 +6180,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev, >>> default: >>> break; >>> } >>> + amdgpu_gfx_off_ctrl(adev, true); >>> >>> return 0; >>> } >>> @@ -6183,6 +6191,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, >>> unsigned type, >>> enum amdgpu_interrupt_state state) >>> { >>> + amdgpu_gfx_off_ctrl(adev, false); >>> switch (type) { >>> case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: >>> gfx_v9_0_set_gfx_eop_interrupt_state(adev, state); >>> @@ -6214,6 +6223,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev, >>> default: >>> break; >>> } >>> + amdgpu_gfx_off_ctrl(adev, true); >>> return 0; >>> } >>> >>