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[2001:4c4e:24da:f700:36af:90f4:d5fb:1eff]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b65eb525d1asm1025062366b.58.2025.10.21.02.23.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Oct 2025 02:23:42 -0700 (PDT) Message-ID: <44ecb43a-5f6e-440e-9e16-f56ca697eed4@gmail.com> Date: Tue, 21 Oct 2025 11:23:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring To: Rodrigo Siqueira , Alex Deucher , =?UTF-8?Q?Christian_K=C3=B6nig?= Cc: amd-gfx@lists.freedesktop.org, kernel-dev@igalia.com References: <20251020194631.102260-1-siqueira@igalia.com> <20251020194631.102260-2-siqueira@igalia.com> Content-Language: en-US From: =?UTF-8?Q?Timur_Krist=C3=B3f?= In-Reply-To: <20251020194631.102260-2-siqueira@igalia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 10/20/25 21:38, Rodrigo Siqueira wrote: > Expand the kernel-doc about amdgpu_ring and add some tiny improvements. > > Cc: Alex Deucher > Cc: Christian König > Cc: Timur Kristóf > Signed-off-by: Rodrigo Siqueira > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 15 ++++++++++++--- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++ > 2 files changed, 14 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > index 5ec5c3ff22bb..29de8dbe2917 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > @@ -75,8 +75,16 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type) > * @ring: amdgpu_ring structure holding ring information > * @ndw: number of dwords to allocate in the ring buffer > * > - * Allocate @ndw dwords in the ring buffer (all asics). > - * Returns 0 on success, error on failure. > + * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When > + * inspecting the code, you may encounter places where this function is invoked > + * like this: amdgpu_ring_alloc(ring, X + Y + Z), where X, Y, and Z are integer > + * numbers. The idea of using each integer addition instead of the final result > + * is to explicitly indicate each block of operation that will be inserted into > + * the ring. To clarify this further, I recommend using the term "packet" instead of "block of operation". > + * > + * Returns: > + * 0 on success, otherwise -ENOMEM if it tries to allocate more than the > + * maximum dword allowed for one submission. > */ > int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw) > { > @@ -122,7 +130,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw) > ring->funcs->begin_use(ring); > } > > -/** amdgpu_ring_insert_nop - insert NOP packets > +/** > + * amdgpu_ring_insert_nop - insert NOP packets > * > * @ring: amdgpu_ring structure holding ring information > * @count: the number of NOP packets to insert > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > index 87b962df5460..e83589619a92 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level { > #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) > #define AMDGPU_FENCE_FLAG_INT (1 << 1) > #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) > + > +/* Ensure the execution in case of preemption or reset */ > #define AMDGPU_FENCE_FLAG_EXEC (1 << 3) > > #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)