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[94.27.159.74]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47aa039ad21sm34038875f8f.20.2026.07.07.08.14.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jul 2026 08:14:01 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: Alex Deucher Cc: amd-gfx@lists.freedesktop.org, Alex Deucher Subject: Re: [PATCH 1/4] drm/gfx10: Program DB_RING_CONTROL Date: Tue, 07 Jul 2026 17:14:00 +0200 Message-ID: <4904707.vXUDI8C0e8@timur-hyperion> In-Reply-To: References: <20260626204101.31172-1-alexander.deucher@amd.com> <14526594.2vocr9iq0E@timur-max> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Tuesday, July 7, 2026 3:44:28=E2=80=AFPM Central European Summer Time Al= ex Deucher=20 wrote: > On Tue, Jul 7, 2026 at 4:06=E2=80=AFAM Timur Krist=C3=B3f =20 wrote: > > On 2026. j=C3=BAnius 26., p=C3=A9ntek 22:40:58 k=C3=B6z=C3=A9p-eur=C3= =B3pai ny=C3=A1ri id=C5=91 Alex Deucher > >=20 > > wrote: > > > This is needed to allocate occlusion counters across > > > both gfx pipes. > > >=20 > > > Fixes: b7a1a0ef12b8 ("drm/amd/amdgpu: add pipe1 hardware support") > > > Signed-off-by: Alex Deucher > > > --- > > >=20 > > > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ > > > 1 file changed, 3 insertions(+) > > >=20 > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > > > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index > > > d72ecf5dab09e..6ff7a8a700939 > > > 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > > > @@ -5352,6 +5352,9 @@ static void gfx_v10_0_constants_init(struct > > > amdgpu_device *adev) gfx_v10_0_get_tcc_info(adev); > > >=20 > > > adev->gfx.config.pa_sc_tile_steering_override =3D > > > =20 > > > gfx_v10_0_init_pa_sc_tile_steering_override(adev); > > >=20 > > > + /* program DB_RING_CONTROL for multiple GFX pipes */ > > > + WREG32_FIELD15(GC, 0, DB_RING_CONTROL, COUNTER_CONTROL, > > > + (adev->gfx.me.num_pipe_per_me > 1) ? 0 : 1); > >=20 > > Hi Alex, > >=20 > > Why do you set this to zero when the number of pipes is more than 1? > > Wouldn't it need to be the other way around and set to the number of pi= pes > > (or number of rings)? >=20 > The hardware default is 1. The other settings are as follows for this > field: 0 - split occlusion counters between gfx pipes > 1 - all occlusion counters to pipe 0 > 2 - all occlusion counters to pipe 1 >=20 I see, thanks! Could you please mention that in a comment or maybe add an enum for the=20 possible values of that field? With that, the series is: Reviewed-by: Timur Krist=C3=B3f > >=20 > > > /* XXX SH_MEM regs */ > > > /* where to put LDS, scratch, GPUVM in FSA64 space */