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[142.127.77.63]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-7bfa70d3ec9sm176452137.11.2026.09.30.11.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 11:57:29 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, sunpeng.li@amd.com Cc: harry.wentland@amd.com, alex.hung@amd.com, chiahsuan.chung@amd.com, ray.wu@amd.com, Leo Li , stable@vger.kernel.org Subject: Re: [PATCH] drm/amd/display: disable self-refresh on tearing flips Date: Wed, 30 Sep 2026 14:57:27 -0400 Message-ID: <4c1BfmguQ8O9e4vVyhq5cw@gmail.com> In-Reply-To: <20260930163222.557757-1-sunpeng.li@amd.com> References: <20260930163222.557757-1-sunpeng.li@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. szeptember 30., szerda 12:30:52 keleti =C3=A1llamokbeli ny=C3=A1ri= id=C5=91=20 sunpeng.li@amd.com wrote: > From: Leo Li >=20 > [Why & How] >=20 > Immediate (tearing) flips breaks self refresh state machine assumptions, > so disable PSR/Replay for them. >=20 > Cc: stable@vger.kernel.org > Signed-off-by: Leo Li Patch fixes tearing updates on Strix Halo. Tested-by: Timur Krist=C3=B3f > --- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) >=20 > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index > 6e5dbe0bd82e5..d4c814eeb56d6 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -3764,6 +3764,13 @@ VISIBLE_IF_KUNIT void > amdgpu_dm_enable_self_refresh(struct amdgpu_display_manage struct > amdgpu_dm_connector *aconn =3D > (struct amdgpu_dm_connector *)acrtc_state->stream- >dm_stream_context; >=20 > + if (!acrtc_state->base.async_flip) { > + amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false, > + psr_event_immediate_flip, false); > + amdgpu_dm_replay_set_event(dm, acrtc_state->stream,=20 false, > + replay_event_immediate_flip, false); > + } > + > /* Decrement skip count when SR is enabled and we're doing fast=20 updates. > */ if (acrtc_state->update_type =3D=3D UPDATE_TYPE_FAST && > (psr->psr_feature_enabled || pr->replay_feature_enabled)) { > @@ -4218,6 +4225,18 @@ static void amdgpu_dm_commit_planes(struct > drm_atomic_commit *state, spin_unlock_irqrestore(&pcrtc->dev->event_lock, > flags); > } > mutex_lock(&dm->dc_lock); > + /* > + * Tearing (immediate) flips cannot work with panel self- refresh > + * features. The event is cleared by > + * amdgpu_dm_enable_self_refresh() once async flips stop. > + */ > + if (immediate_flip) { > + dc_exit_ips_for_hw_access(dm->dc); > + amdgpu_dm_psr_set_event(dm, acrtc_state- >stream, true, > + psr_event_immediate_flip, true); > + amdgpu_dm_replay_set_event(dm, acrtc_state- >stream, true, > + replay_event_immediate_flip, true); > + } > update_planes_and_stream_adapter(dm->dc, > planes_count, > acrtc_state->stream,