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From: "Kuehling, Felix" <Felix.Kuehling-5C7GfCeVMHo@public.gmane.org>
To: Alex Deucher
	<alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"Yang, Philip" <Philip.Yang-5C7GfCeVMHo@public.gmane.org>
Cc: amd-gfx list <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Subject: Re: [PATCH] drm/amdgpu: enable paging queue doorbell support v3
Date: Fri, 16 Nov 2018 22:58:50 +0000	[thread overview]
Message-ID: <549a3f39-2be2-9f0c-8317-a4a69371c9f3@amd.com> (raw)
In-Reply-To: <CADnq5_M_FFga1hxj187yt0bf2DPLNj-OggUe-B=9TDYYRdMYVA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>


On 2018-11-16 4:35 p.m., Alex Deucher wrote:
>> +                       ring->doorbell_index += 0x400;
> I don't quite understand how this works.  Why don't we have to adjust
> the doorbell range registers in the nbio code?

NBIO only looks at the lower 12 bits of the doorbell address. So adding
0x400 dwords or 0x1000 bytes has no effect on the doorbell routing.

That's also how we can use SDMA doorbells in our per-process doorbell
pages at higher addresses.

Regards,
  Felix


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      parent reply	other threads:[~2018-11-16 22:58 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-16 19:08 [PATCH] drm/amdgpu: enable paging queue doorbell support v3 Yang, Philip
     [not found] ` <20181116190819.28112-1-Philip.Yang-5C7GfCeVMHo@public.gmane.org>
2018-11-16 19:16   ` Kuehling, Felix
2018-11-16 21:35   ` Alex Deucher
     [not found]     ` <CADnq5_M_FFga1hxj187yt0bf2DPLNj-OggUe-B=9TDYYRdMYVA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-11-16 22:38       ` Yang, Philip
2018-11-16 22:58       ` Kuehling, Felix [this message]

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