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([2a02:908:1256:79a0:95df:c673:e23c:7b70]) by smtp.gmail.com with ESMTPSA id b18-20020a1709063cb200b0072afb23fb9esm3652672ejh.16.2022.07.08.03.03.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Jul 2022 03:03:05 -0700 (PDT) Message-ID: <57e44bdf-9bea-4c9b-0b05-ff0b68fcf44c@gmail.com> Date: Fri, 8 Jul 2022 12:03:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH] drm/amdgpu/gmc10: adjust gart size for parts that support S/G display Content-Language: en-US To: Alex Deucher , amd-gfx@lists.freedesktop.org References: <20220707205530.899499-1-alexander.deucher@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= In-Reply-To: <20220707205530.899499-1-alexander.deucher@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 07.07.22 um 22:55 schrieb Alex Deucher: > For GMC 10 parts which support scatter/gather display (display > from system memory), we should allocate a larger gart size > to better handler larger displays. This mirrors what we already > do for GMC 9 parts. > > v2: fix typo (Alex) > > Signed-off-by: Alex Deucher Acked-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c > index 25d5743ae91b..1772f006c61a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c > @@ -834,10 +834,21 @@ static int gmc_v10_0_mc_init(struct amdgpu_device *adev) > adev->gmc.visible_vram_size = adev->gmc.real_vram_size; > > /* set the gart size */ > - if (amdgpu_gart_size == -1) > - adev->gmc.gart_size = 512ULL << 20; > - else > + if (amdgpu_gart_size == -1) { > + switch (adev->ip_versions[GC_HWIP][0]) { > + default: > + adev->gmc.gart_size = 512ULL << 20; > + break; > + case IP_VERSION(10, 3, 1): /* DCE SG support */ > + case IP_VERSION(10, 3, 3): /* DCE SG support */ > + case IP_VERSION(10, 3, 6): /* DCE SG support */ > + case IP_VERSION(10, 3, 7): /* DCE SG support */ > + adev->gmc.gart_size = 1024ULL << 20; > + break; > + } > + } else { > adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; > + } > > gmc_v10_0_vram_gtt_location(adev, &adev->gmc); >