>From 9110b529019fbac27a95ce3090d305c528e0999b Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Thu, 22 Sep 2016 14:50:16 +0800 Subject: [PATCH 1/2] amdgpu: add new semaphore support Change-Id: Iae7e4157d6184dab1cd4a944ae9cb803f9b11670 Signed-off-by: Chunming Zhou --- amdgpu/amdgpu.h | 74 +++++++++++++++++++++++++++++++++++++++ amdgpu/amdgpu_cs.c | 90 ++++++++++++++++++++++++++++++++++++++++++++++++ include/drm/amdgpu_drm.h | 29 ++++++++++++++++ 3 files changed, 193 insertions(+) diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index 525bf8e..bd6265d 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -137,6 +137,12 @@ typedef struct amdgpu_va *amdgpu_va_handle; */ typedef struct amdgpu_semaphore *amdgpu_semaphore_handle; +/** + * Define handle for sem file + */ +typedef int amdgpu_sem_handle; + + /*--------------------------------------------------------------------------*/ /* -------------------------- Structures ---------------------------------- */ /*--------------------------------------------------------------------------*/ @@ -1529,6 +1535,74 @@ int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem); /** + * create sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + * \param sem - \c [out] sem handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_create_sem(amdgpu_device_handle dev, + amdgpu_sem_handle *sem); + +/** + * signal sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + * \param context - \c [in] GPU Context + * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* + * \param ip_instance - \c [in] Index of the IP block of the same type + * \param ring - \c [in] Specify ring index of the IP + * \param sem - \c [out] sem handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + */ +int amdgpu_cs_signal_sem(amdgpu_device_handle dev, + amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_sem_handle sem); + +/** + * wait sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + * \param context - \c [in] GPU Context + * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_* + * \param ip_instance - \c [in] Index of the IP block of the same type + * \param ring - \c [in] Specify ring index of the IP + * \param sem - \c [out] sem handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_cs_wait_sem(amdgpu_device_handle dev, + amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_sem_handle sem); + +/** + * destroy sem + * + * \param dev - [in] Device handle. See #amdgpu_device_initialize() + * \param sem - \c [out] sem handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + */ +int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, + amdgpu_sem_handle sem); + +/** * Get the ASIC marketing name * * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 73fde25..1018f76 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -25,6 +25,8 @@ #include "config.h" #endif +#include +#include #include #include #include @@ -639,3 +641,91 @@ int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem) { return amdgpu_cs_unreference_sem(sem); } + +int amdgpu_cs_create_sem(amdgpu_device_handle dev, + amdgpu_sem_handle *sem) +{ + union drm_amdgpu_sem args; + int r; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_CREATE_SEM; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); + if (r) + return r; + + *sem = args.out.fd; + + return 0; +} + +int amdgpu_cs_signal_sem(amdgpu_device_handle dev, + amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_sem_handle sem) +{ + union drm_amdgpu_sem args; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_SIGNAL_SEM; + args.in.ctx_id = ctx->id; + args.in.ip_type = ip_type; + args.in.ip_instance = ip_instance; + args.in.ring = ring; + args.in.fd = sem; + return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); +} + +int amdgpu_cs_wait_sem(amdgpu_device_handle dev, + amdgpu_context_handle ctx, + uint32_t ip_type, + uint32_t ip_instance, + uint32_t ring, + amdgpu_sem_handle sem) +{ + union drm_amdgpu_sem args; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_WAIT_SEM; + args.in.ctx_id = ctx->id; + args.in.ip_type = ip_type; + args.in.ip_instance = ip_instance; + args.in.ring = ring; + args.in.fd = sem; + args.in.seq = 0; + return drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); +} + +int amdgpu_cs_destroy_sem(amdgpu_device_handle dev, + amdgpu_sem_handle sem) +{ + union drm_amdgpu_sem args; + int r; + + if (NULL == dev) + return -EINVAL; + + /* Create the context */ + memset(&args, 0, sizeof(args)); + args.in.op = AMDGPU_SEM_OP_DESTROY_SEM; + args.in.fd = sem; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_SEM, &args, sizeof(args)); + if (r) + return r; + close(sem); + return 0; +} diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index bb60504..cb784fd 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -47,6 +47,7 @@ #define DRM_AMDGPU_GEM_OP 0x10 #define DRM_AMDGPU_GEM_USERPTR 0x11 /* hybrid specific ioctls */ +#define DRM_AMDGPU_SEM 0x5b #define DRM_AMDGPU_GEM_DGMA 0x5c #define DRM_AMDGPU_FREESYNC 0x5d #define DRM_AMDGPU_WAIT_FENCES 0x5e @@ -69,6 +70,7 @@ #define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync) #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) #define DRM_IOCTL_AMDGPU_GEM_FIND_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_FIND_BO, struct drm_amdgpu_gem_find_bo) +#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 @@ -193,6 +195,33 @@ union drm_amdgpu_ctx { union drm_amdgpu_ctx_out out; }; +/* sync file related */ +#define AMDGPU_SEM_OP_CREATE_SEM 1 +#define AMDGPU_SEM_OP_WAIT_SEM 2 +#define AMDGPU_SEM_OP_SIGNAL_SEM 3 +#define AMDGPU_SEM_OP_DESTROY_SEM 4 + +struct drm_amdgpu_sem_in { + /** AMDGPU_SEM_OP_* */ + uint32_t op; + int fd; + uint32_t ctx_id; + uint32_t ip_type; + uint32_t ip_instance; + uint32_t ring; + uint64_t seq; +}; + +union drm_amdgpu_sem_out { + int fd; + uint32_t _pad; +}; + +union drm_amdgpu_sem { + struct drm_amdgpu_sem_in in; + union drm_amdgpu_sem_out out; +}; + /* * This is not a reliable API and you should expect it to fail for any * number of reasons and have fallback path that do not use userptr to -- 1.9.1