From: "Zhang, Jerry (Junwei)" <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
To: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>,
"amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org"
<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: "Laktyushkin, Dmytro" <Dmytro.Laktyushkin-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH 09/34] drm/amd/display: fix lexa bw bounding box
Date: Wed, 21 Mar 2018 09:27:35 +0800 [thread overview]
Message-ID: <5AB1B507.6060208@amd.com> (raw)
In-Reply-To: <20180320191259.14453-10-harry.wentland-5C7GfCeVMHo@public.gmane.org>
Please adhere to the naming of Polaris12 in commit log as well.
thanks.
Jerry
On 03/21/2018 03:12 AM, Harry Wentland wrote:
> From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
>
> Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
> Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> Acked-by: Harry Wentland <harry.wentland@amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 121 ++++++++++++++++++++++-
> drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 1 +
> 2 files changed, 120 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> index 0cbab81ab304..3d05e82652af 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c
> @@ -52,10 +52,11 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi
> return BW_CALCS_VERSION_CARRIZO;
>
> case FAMILY_VI:
> + if (ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
> + return BW_CALCS_VERSION_LEXA;
> if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
> return BW_CALCS_VERSION_POLARIS10;
> - if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
> - ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev))
> + if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
> return BW_CALCS_VERSION_POLARIS11;
> return BW_CALCS_VERSION_INVALID;
>
> @@ -2373,6 +2374,122 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
> dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
> dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
> break;
> + case BW_CALCS_VERSION_LEXA:
> + vbios.memory_type = bw_def_gddr5;
> + vbios.dram_channel_width_in_bits = 32;
> + vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
> + vbios.number_of_dram_banks = 8;
> + vbios.high_yclk = bw_int_to_fixed(6000);
> + vbios.mid_yclk = bw_int_to_fixed(3200);
> + vbios.low_yclk = bw_int_to_fixed(1000);
> + vbios.low_sclk = bw_int_to_fixed(678);
> + vbios.mid1_sclk = bw_int_to_fixed(864);
> + vbios.mid2_sclk = bw_int_to_fixed(900);
> + vbios.mid3_sclk = bw_int_to_fixed(920);
> + vbios.mid4_sclk = bw_int_to_fixed(940);
> + vbios.mid5_sclk = bw_int_to_fixed(960);
> + vbios.mid6_sclk = bw_int_to_fixed(980);
> + vbios.high_sclk = bw_int_to_fixed(1049);
> + vbios.low_voltage_max_dispclk = bw_int_to_fixed(459);
> + vbios.mid_voltage_max_dispclk = bw_int_to_fixed(654);
> + vbios.high_voltage_max_dispclk = bw_int_to_fixed(1108);
> + vbios.low_voltage_max_phyclk = bw_int_to_fixed(540);
> + vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810);
> + vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
> + vbios.data_return_bus_width = bw_int_to_fixed(32);
> + vbios.trc = bw_int_to_fixed(48);
> + if (vbios.number_of_dram_channels == 2) // 64-bit
> + vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
> + else
> + vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
> + vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
> + vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
> + vbios.nbp_state_change_latency = bw_int_to_fixed(250);
> + vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10);
> + vbios.scatter_gather_enable = false;
> + vbios.down_spread_percentage = bw_frc_to_fixed(5, 10);
> + vbios.cursor_width = 32;
> + vbios.average_compression_rate = 4;
> + vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 256;
> + vbios.blackout_duration = bw_int_to_fixed(0); /* us */
> + vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0);
> +
> + dceip.max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation = 100;
> + dceip.max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation = 100;
> + dceip.percent_of_ideal_port_bw_received_after_urgent_latency = 100;
> + dceip.large_cursor = false;
> + dceip.dmif_request_buffer_size = bw_int_to_fixed(768);
> + dceip.dmif_pipe_en_fbc_chunk_tracker = false;
> + dceip.cursor_max_outstanding_group_num = 1;
> + dceip.lines_interleaved_into_lb = 2;
> + dceip.chunk_width = 256;
> + dceip.number_of_graphics_pipes = 5;
> + dceip.number_of_underlay_pipes = 0;
> + dceip.low_power_tiling_mode = 0;
> + dceip.display_write_back_supported = true;
> + dceip.argb_compression_support = true;
> + dceip.underlay_vscaler_efficiency6_bit_per_component =
> + bw_frc_to_fixed(35556, 10000);
> + dceip.underlay_vscaler_efficiency8_bit_per_component =
> + bw_frc_to_fixed(34286, 10000);
> + dceip.underlay_vscaler_efficiency10_bit_per_component =
> + bw_frc_to_fixed(32, 10);
> + dceip.underlay_vscaler_efficiency12_bit_per_component =
> + bw_int_to_fixed(3);
> + dceip.graphics_vscaler_efficiency6_bit_per_component =
> + bw_frc_to_fixed(35, 10);
> + dceip.graphics_vscaler_efficiency8_bit_per_component =
> + bw_frc_to_fixed(34286, 10000);
> + dceip.graphics_vscaler_efficiency10_bit_per_component =
> + bw_frc_to_fixed(32, 10);
> + dceip.graphics_vscaler_efficiency12_bit_per_component =
> + bw_int_to_fixed(3);
> + dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3);
> + dceip.max_dmif_buffer_allocated = 4;
> + dceip.graphics_dmif_size = 12288;
> + dceip.underlay_luma_dmif_size = 19456;
> + dceip.underlay_chroma_dmif_size = 23552;
> + dceip.pre_downscaler_enabled = true;
> + dceip.underlay_downscale_prefetch_enabled = true;
> + dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1);
> + dceip.lb_size_per_component444 = bw_int_to_fixed(245952);
> + dceip.graphics_lb_nodownscaling_multi_line_prefetching = true;
> + dceip.stutter_and_dram_clock_state_change_gated_before_cursor =
> + bw_int_to_fixed(1);
> + dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed(
> + 82176);
> + dceip.underlay420_chroma_lb_size_per_component =
> + bw_int_to_fixed(164352);
> + dceip.underlay422_lb_size_per_component = bw_int_to_fixed(
> + 82176);
> + dceip.cursor_chunk_width = bw_int_to_fixed(64);
> + dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4);
> + dceip.underlay_maximum_width_efficient_for_tiling =
> + bw_int_to_fixed(1920);
> + dceip.underlay_maximum_height_efficient_for_tiling =
> + bw_int_to_fixed(1080);
> + dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display =
> + bw_frc_to_fixed(3, 10);
> + dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation =
> + bw_int_to_fixed(25);
> + dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed(
> + 2);
> + dceip.maximum_total_outstanding_pte_requests_allowed_by_saw =
> + bw_int_to_fixed(128);
> + dceip.limit_excessive_outstanding_dmif_requests = true;
> + dceip.linear_mode_line_request_alternation_slice =
> + bw_int_to_fixed(64);
> + dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode =
> + 32;
> + dceip.display_write_back420_luma_mcifwr_buffer_size = 12288;
> + dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192;
> + dceip.request_efficiency = bw_frc_to_fixed(8, 10);
> + dceip.dispclk_per_request = bw_int_to_fixed(2);
> + dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100);
> + dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100);
> + dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2;
> + dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0);
> + break;
> case BW_CALCS_VERSION_STONEY:
> vbios.memory_type = bw_def_gddr5;
> vbios.dram_channel_width_in_bits = 64;
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
> index a9bfe9ff8ce6..c8401b92b8af 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h
> @@ -42,6 +42,7 @@ enum bw_calcs_version {
> BW_CALCS_VERSION_CARRIZO,
> BW_CALCS_VERSION_POLARIS10,
> BW_CALCS_VERSION_POLARIS11,
> + BW_CALCS_VERSION_LEXA,
> BW_CALCS_VERSION_STONEY,
> BW_CALCS_VERSION_VEGA10
> };
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
next prev parent reply other threads:[~2018-03-21 1:27 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-20 19:12 [PATCH 00/34] DC Patches Mar 20, 2018 Harry Wentland
[not found] ` <20180320191259.14453-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-20 19:12 ` [PATCH 01/34] drm/amd/display: correct the condition in setting cursor not visible beyond left edge Harry Wentland
2018-03-20 19:12 ` [PATCH 02/34] drm/amd/display: dal 3.1.39 Harry Wentland
2018-03-20 19:12 ` [PATCH 03/34] drm/amd/display: Allow truncation to 10 bits Harry Wentland
2018-03-20 19:12 ` [PATCH 04/34] drm/amd/display: Fix FMT truncation programming Harry Wentland
2018-03-20 19:12 ` [PATCH 05/34] drm/amd/display: We shouldn't set format_default on plane as atomic driver Harry Wentland
2018-03-20 19:12 ` [PATCH 06/34] drm/amd/display: Retry when read dpcd caps failed Harry Wentland
2018-03-20 19:12 ` [PATCH 07/34] drm/amd/display: Add one to EDID's audio channel count when passing to DC Harry Wentland
2018-03-20 19:12 ` [PATCH 08/34] drm/amd/display: Update ASIC header files Harry Wentland
2018-03-20 19:12 ` [PATCH 09/34] drm/amd/display: fix lexa bw bounding box Harry Wentland
[not found] ` <20180320191259.14453-10-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-21 1:27 ` Zhang, Jerry (Junwei) [this message]
2018-03-22 18:39 ` [PATCH v2] drm/amd/display: fix Polaris 12 " Harry Wentland
[not found] ` <20180322183957.11419-1-harry.wentland-5C7GfCeVMHo@public.gmane.org>
2018-03-22 18:51 ` Deucher, Alexander
2018-03-20 19:12 ` [PATCH 10/34] drm/amd/display: Rename feature-specific register address init macro Harry Wentland
2018-03-20 19:12 ` [PATCH 11/34] drm/amd/display: Don't read EDID in atomic_check Harry Wentland
2018-03-20 19:12 ` [PATCH 12/34] drm/amd/display: add mpc to dtn log Harry Wentland
2018-03-20 19:12 ` [PATCH 13/34] drm/amd/display: Add debug prints for bandwidth calculations Harry Wentland
2018-03-20 19:12 ` [PATCH 14/34] drm/amd/display: Don't call amdgpu_dm_display_resume as it doesn't exist Harry Wentland
2018-03-20 19:12 ` [PATCH 15/34] drm/amd/display: Adding stutter entry wm to dce bw struct Harry Wentland
2018-03-20 19:12 ` [PATCH 16/34] drm/amd/display: Change wb_h/vratio to double Harry Wentland
2018-03-20 19:12 ` [PATCH 17/34] drm/amd/display: drop dc_validate_guaranteed Harry Wentland
2018-03-20 19:12 ` [PATCH 18/34] drm/amd/display: Implementing new bandwidth registers for DCE120 Harry Wentland
2018-03-20 19:12 ` [PATCH 19/34] drm/amd/display: dal 3.1.40 Harry Wentland
2018-03-20 19:12 ` [PATCH 20/34] drm/amd/display: align dtn logs and add mpc idle bit print Harry Wentland
2018-03-20 19:12 ` [PATCH 21/34] drm/amd/display: add assert in enable FBC Harry Wentland
2018-03-20 19:12 ` [PATCH 22/34] drm/amd/display: Separate mem input constuctors for dce 112 and 120 Harry Wentland
2018-03-20 19:12 ` [PATCH 23/34] drm/amd/display: Only update mpc blend config if not full update Harry Wentland
2018-03-20 19:12 ` [PATCH 24/34] drm/amd/display: hide inconsistent mpcc programming from dtn log Harry Wentland
2018-03-20 19:12 ` [PATCH 25/34] drm/amd/display: Add dc_lut_mode enum Harry Wentland
2018-03-20 19:12 ` [PATCH 26/34] drm/amd/display: Correct print types in DC_LOGS Harry Wentland
2018-03-20 19:12 ` [PATCH 27/34] drm/amd/display: Add num_active_wb to DML Harry Wentland
2018-03-20 19:12 ` [PATCH 28/34] drm/amd/display: Add double buffer machanism to ICSC Harry Wentland
2018-03-20 19:12 ` [PATCH 29/34] drm/amd/display: Couple bug fixes in stats module Harry Wentland
2018-03-20 19:12 ` [PATCH 30/34] drm/amd/display: Rename encoder_info_packet to dc_info_packet Harry Wentland
2018-03-20 19:12 ` [PATCH 31/34] drm/amd/display: Add vline IRQ programming for DCN Harry Wentland
2018-03-20 19:12 ` [PATCH 32/34] drm/amd/display: Add double buffer machanism to OCSC Harry Wentland
2018-03-20 19:12 ` [PATCH 33/34] drm/amd/display: Only program MSA_TIMING_PARAM if it changed Harry Wentland
2018-03-20 19:12 ` [PATCH 34/34] drm/amd/display: Move commit_planes_to_stream to amdgpu_dm Harry Wentland
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5AB1B507.6060208@amd.com \
--to=jerry.zhang-5c7gfcevmho@public.gmane.org \
--cc=Dmytro.Laktyushkin-5C7GfCeVMHo@public.gmane.org \
--cc=amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org \
--cc=harry.wentland-5C7GfCeVMHo@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox