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d="scan'208";a="193379508" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.1]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2025 06:10:37 -0800 From: Jani Nikula To: Yaroslav Bolyukin , Ville =?utf-8?B?U3lyasOkbMOk?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , Christian =?utf-8?Q?K=C3=B6nig?= , Wayne Lin , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yaroslav Bolyukin Subject: Re: [PATCH v6 3/7] drm/edid: MSO should only be used for non-eDP displays In-Reply-To: <20251126065126.54016-4-iam@lach.pw> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251126065126.54016-1-iam@lach.pw> <20251126065126.54016-4-iam@lach.pw> Date: Wed, 26 Nov 2025 16:10:34 +0200 Message-ID: <5be6faede273533b88e592bd25776b639d2eeb9f@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Wed, 26 Nov 2025, Yaroslav Bolyukin wrote: > As per DisplayID v2.1a spec: > If Offset 06h[2:0] is programmed to 001b (External DisplayPort), this > field shall be cleared to 00b (Not supported). > > Link: https://lore.kernel.org/lkml/3abc1087618c822e5676e67a3ec2e64e506dc5ec@intel.com/ > Signed-off-by: Yaroslav Bolyukin > --- > drivers/gpu/drm/drm_displayid_internal.h | 4 +++ > drivers/gpu/drm/drm_edid.c | 36 +++++++++++++++--------- > 2 files changed, 27 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h > index 5b1b32f73516..72f107ae832f 100644 > --- a/drivers/gpu/drm/drm_displayid_internal.h > +++ b/drivers/gpu/drm/drm_displayid_internal.h > @@ -142,9 +142,13 @@ struct displayid_formula_timing_block { > struct displayid_formula_timings_9 timings[]; > } __packed; > > +#define DISPLAYID_VESA_DP_TYPE GENMASK(2, 0) > #define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0) > #define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5) > > +#define DISPLAYID_VESA_DP_TYPE_EDP 0 > +#define DISPLAYID_VESA_DP_TYPE_DP 1 > + > struct displayid_vesa_vendor_specific_block { > struct displayid_block base; > u8 oui[3]; > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index a52fd6de9327..348aa31aea1b 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -6533,6 +6533,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector, > struct displayid_vesa_vendor_specific_block *vesa = > (struct displayid_vesa_vendor_specific_block *)block; > struct drm_display_info *info = &connector->display_info; > + int dp_type; > > if (block->num_bytes < 3) { > drm_dbg_kms(connector->dev, > @@ -6551,20 +6552,29 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector, > return; > } > > - switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { > - default: > - drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", > + dp_type = FIELD_GET(DISPLAYID_VESA_DP_TYPE, vesa->data_structure_type); > + if (dp_type > 1) { > + drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved dp type value\n", > connector->base.id, connector->name); > - fallthrough; > - case 0: > - info->mso_stream_count = 0; > - break; > - case 1: > - info->mso_stream_count = 2; /* 2 or 4 links */ > - break; > - case 2: > - info->mso_stream_count = 4; /* 4 links */ > - break; > + } > + > + /* MSO is not supported for eDP */ > + if (dp_type != DISPLAYID_VESA_DP_TYPE_EDP) { MSO is *only* supported on eDP, not the other way round! BR, Jani. > + switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { > + default: > + drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", > + connector->base.id, connector->name); > + fallthrough; > + case 0: > + info->mso_stream_count = 0; > + break; > + case 1: > + info->mso_stream_count = 2; /* 2 or 4 links */ > + break; > + case 2: > + info->mso_stream_count = 4; /* 4 links */ > + break; > + } > } > > if (info->mso_stream_count) { -- Jani Nikula, Intel