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d="scan'208";a="197450191" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.1]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2025 06:59:13 -0800 From: Jani Nikula To: Yaroslav , Yaroslav Bolyukin , Ville =?utf-8?B?U3lyasOkbMOk?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , Christian =?utf-8?Q?K=C3=B6nig?= , Wayne Lin , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251126065126.54016-1-iam@lach.pw> <20251126065126.54016-3-iam@lach.pw> <68c55e772424f8e001898cdd1edcf4856820461e@intel.com> Date: Wed, 26 Nov 2025 16:59:09 +0200 Message-ID: <61a482c23a81dc29f1fb793064c7238a98cf0143@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Wed, 26 Nov 2025, Yaroslav wrote: > On 2025-11-26 15:08, Jani Nikula wrote: >> On Wed, 26 Nov 2025, Jani Nikula wrote: >>> On Wed, 26 Nov 2025, Yaroslav Bolyukin wrote: >>>> Current VESA vendor-specific block parsing expects real block size to be >>>> the same as the defined struct size, use real offsets in conditionals >>>> instead to add struct fields in future commits. >>>> >>>> Signed-off-by: Yaroslav Bolyukin >>> >>> I think this is something we want to backport, since MSO would break >>> with bigger vendor-specific blocks, and that leads to black screens on >>> MSO displays. >>> >>> Cc: stable@vger.kernel.org >>> Reviewed-by: Jani Nikula >> >> Oops, I'll take that back. >> >>> >>>> --- >>>> drivers/gpu/drm/drm_edid.c | 28 ++++++++++++---------------- >>>> 1 file changed, 12 insertions(+), 16 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c >>>> index 64f7a94dd9e4..a52fd6de9327 100644 >>>> --- a/drivers/gpu/drm/drm_edid.c >>>> +++ b/drivers/gpu/drm/drm_edid.c >>>> @@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector, >>>> if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) >>>> return; >>>> >>>> - if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { >>>> + if (block->num_bytes < 5) { >>>> drm_dbg_kms(connector->dev, >>>> "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", >>>> connector->base.id, connector->name); >>>> @@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector, >>>> break; >>>> } >>>> >>>> - if (!info->mso_stream_count) { >>>> - info->mso_pixel_overlap = 0; >> >> This is no longer cleared for !info->mso_stream_count. >> >> Perhaps the code could be reorganized to handle it better. > > It defaults to zero due to drm_reset_display_info() Yes, and the code above the context initializes it from the vendor block. > >>>> - return; >>>> - } >>>> - >>>> - info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); >>>> - if (info->mso_pixel_overlap > 8) { >>>> + if (info->mso_stream_count) { >>>> + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); >>>> + if (info->mso_pixel_overlap > 8) { >>>> + drm_dbg_kms(connector->dev, >>>> + "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", >>>> + connector->base.id, connector->name, >>>> + info->mso_pixel_overlap); >>>> + info->mso_pixel_overlap = 8; >>>> + } >>>> drm_dbg_kms(connector->dev, >>>> - "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", >>>> + "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", >>>> connector->base.id, connector->name, >>>> - info->mso_pixel_overlap); >>>> - info->mso_pixel_overlap = 8; >>>> + info->mso_stream_count, info->mso_pixel_overlap); >>>> } >>>> - >>>> - drm_dbg_kms(connector->dev, >>>> - "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", >>>> - connector->base.id, connector->name, >>>> - info->mso_stream_count, info->mso_pixel_overlap); >>>> } >>>> >>>> static void drm_update_vesa_specific_block(struct drm_connector *connector, >> > -- Jani Nikula, Intel