From: "Sharma, Shashank" <shashank.sharma@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v11 00/28] AMDGPU usermode queues
Date: Wed, 25 Sep 2024 11:14:54 +0200 [thread overview]
Message-ID: <69c5664e-6b70-4f69-98bd-b10403b52691@amd.com> (raw)
In-Reply-To: <CADnq5_OzaOWZ4tvN=13oXHc091kFUdtkhz9=R8-eknD1PMhYkw@mail.gmail.com>
On 19/09/2024 18:59, Alex Deucher wrote:
> On Mon, Sep 9, 2024 at 4:07 PM Shashank Sharma <shashank.sharma@amd.com> wrote:
>> This patch series introduces base code of AMDGPU usermode queues for gfx
>> workloads. Usermode queues is a method of GPU workload submission into the
>> graphics hardware without any interaction with kernel/DRM schedulers. In
>> this method, a userspace graphics application can create its own workqueue
>> and submit it directly in the GPU HW.
>>
>> The general idea of how Userqueues are supposed to work:
>> - The application creates the following GPU objetcs:
>> - A queue object to hold the workload packets.
>> - A read pointer object.
>> - A write pointer object.
>> - A doorbell page.
>> - Other supporting buffer objects as per target IP engine (shadow, GDS
>> etc, information available with AMDGPU_INFO_IOCTL)
> the queue, rptr, wptr, and metadata buffers don't have to be separate
> buffers. Userspace could suballocate them out of the same buffer. We
> just need the virtual addresses. However, we need to keep track of
> the GPU virtual addresses used by the user queue for these buffers and
> prevent them from being unmapped until the queue is destroyed, similar
> to what we do on the KFD side. Otherwise, the user could unmap one of
> the buffers and submit work to the user queue which could cause it to
> hang.
Noted, thanks Alex.
> Alex
>
>> - The application picks a 32-bit offset in the doorbell page for this
>> queue.
>> - The application uses the usermode_queue_create IOCTL introduced in
>> this patch, by passing the GPU addresses of these objects (read ptr,
>> write ptr, queue base address, shadow, gds) with doorbell object and
>> 32-bit doorbell offset in the doorbell page.
>> - The kernel creates the queue and maps it in the HW.
>> - The application maps the GPU buffers in process address space.
>> - The application can start submitting the data in the queue as soon as
>> the kernel IOCTL returns.
>> - After filling the workload data in the queue, the app must write the
>> number of dwords added in the queue into the doorbell offset and the
>> WPTR buffer. The GPU will start fetching the data as soon as its done.
>> - This series adds usermode queue support for all three MES based IPs
>> (GFX, SDMA and Compute).
>> - This series also adds eviction fences to handle migration of the
>> userqueue mapped buffers by TTM.
>> - For synchronization of userqueues, we have added a secure semaphores
>> IOCTL which is getting reviewed separately here:
>> https://patchwork.freedesktop.org/patch/611971/
>>
>> libDRM UAPI changes for this series can be found here:
>> (This also contains an example test utility which demonstrates
>> the usage of userqueue UAPI)
>> https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/287
>>
>> MESA changes consuming this series can be seen in the MR here:
>> https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29010
>>
>> Alex Deucher (1):
>> drm/amdgpu: UAPI for user queue management
>>
>> Arvind Yadav (4):
>> drm/amdgpu: enable SDMA usermode queues
>> drm/amdgpu: Add input fence to sync bo unmap
>> drm/amdgpu: fix MES GFX mask
>> Revert "drm/amdgpu: don't allow userspace to create a doorbell BO"
>>
>> Shashank Sharma (18):
>> drm/amdgpu: add usermode queue base code
>> drm/amdgpu: add new IOCTL for usermode queue
>> drm/amdgpu: add helpers to create userqueue object
>> drm/amdgpu: create MES-V11 usermode queue for GFX
>> drm/amdgpu: create context space for usermode queue
>> drm/amdgpu: map usermode queue into MES
>> drm/amdgpu: map wptr BO into GART
>> drm/amdgpu: generate doorbell index for userqueue
>> drm/amdgpu: cleanup leftover queues
>> drm/amdgpu: enable GFX-V11 userqueue support
>> drm/amdgpu: enable compute/gfx usermode queue
>> drm/amdgpu: update userqueue BOs and PDs
>> drm/amdgpu: add kernel config for gfx-userqueue
>> drm/amdgpu: add gfx eviction fence helpers
>> drm/amdgpu: add userqueue suspend/resume functions
>> drm/amdgpu: suspend gfx userqueues
>> drm/amdgpu: resume gfx userqueues
>> Revert "drm/amdgpu/gfx11: only enable CP GFX shadowing on SR-IOV"
>>
>> drivers/gpu/drm/amd/amdgpu/Kconfig | 8 +
>> drivers/gpu/drm/amd/amdgpu/Makefile | 10 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 10 +
>> .../drm/amd/amdgpu/amdgpu_eviction_fence.c | 297 ++++++++
>> .../drm/amd/amdgpu/amdgpu_eviction_fence.h | 67 ++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 68 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 11 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 -
>> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 +-
>> .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.c | 713 ++++++++++++++++++
>> .../gpu/drm/amd/amdgpu/amdgpu_userq_fence.h | 74 ++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 644 ++++++++++++++++
>> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 42 +-
>> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 16 +-
>> .../gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 395 ++++++++++
>> .../gpu/drm/amd/amdgpu/mes_v11_0_userqueue.h | 30 +
>> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 5 +
>> .../gpu/drm/amd/include/amdgpu_userqueue.h | 100 +++
>> drivers/gpu/drm/amd/include/v11_structs.h | 4 +-
>> include/uapi/drm/amdgpu_drm.h | 252 +++++++
>> 22 files changed, 2722 insertions(+), 45 deletions(-)
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_eviction_fence.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.h
>> create mode 100644 drivers/gpu/drm/amd/include/amdgpu_userqueue.h
>>
>> --
>> 2.45.1
>>
prev parent reply other threads:[~2024-09-25 9:15 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-09 20:05 [PATCH v11 00/28] AMDGPU usermode queues Shashank Sharma
2024-09-09 20:05 ` [PATCH v11 01/28] drm/amdgpu: UAPI for user queue management Shashank Sharma
2024-09-09 20:05 ` [PATCH v11 02/28] drm/amdgpu: add usermode queue base code Shashank Sharma
2024-09-09 20:05 ` [PATCH v11 03/28] drm/amdgpu: add new IOCTL for usermode queue Shashank Sharma
2024-09-09 20:05 ` [PATCH v11 04/28] drm/amdgpu: add helpers to create userqueue object Shashank Sharma
2024-09-09 20:05 ` [PATCH v11 05/28] drm/amdgpu: create MES-V11 usermode queue for GFX Shashank Sharma
2024-09-09 20:05 ` [PATCH v11 06/28] drm/amdgpu: create context space for usermode queue Shashank Sharma
2024-10-18 17:39 ` Alex Deucher
2024-09-09 20:05 ` [PATCH v11 07/28] drm/amdgpu: map usermode queue into MES Shashank Sharma
2024-09-09 20:05 ` [PATCH v11 08/28] drm/amdgpu: map wptr BO into GART Shashank Sharma
2024-09-16 12:39 ` Christian König
2024-09-09 20:06 ` [PATCH v11 09/28] drm/amdgpu: generate doorbell index for userqueue Shashank Sharma
2024-09-09 20:06 ` [PATCH v11 10/28] drm/amdgpu: cleanup leftover queues Shashank Sharma
2024-09-09 20:06 ` [PATCH v11 11/28] drm/amdgpu: enable GFX-V11 userqueue support Shashank Sharma
2024-09-09 20:06 ` [PATCH v11 12/28] drm/amdgpu: enable SDMA usermode queues Shashank Sharma
2024-09-09 20:06 ` [PATCH v11 13/28] drm/amdgpu: enable compute/gfx usermode queue Shashank Sharma
2024-09-09 20:06 ` [PATCH v11 14/28] drm/amdgpu: update userqueue BOs and PDs Shashank Sharma
2024-09-09 20:06 ` [PATCH v11 15/28] drm/amdgpu: add kernel config for gfx-userqueue Shashank Sharma
2024-09-09 20:06 ` [PATCH v11 21/28] drm/amdgpu: add gfx eviction fence helpers Shashank Sharma
2024-09-16 14:14 ` Christian König
2024-09-25 9:08 ` Sharma, Shashank
2024-09-09 20:06 ` [PATCH v11 22/28] drm/amdgpu: add userqueue suspend/resume functions Shashank Sharma
2024-09-09 20:06 ` [PATCH v11 23/28] drm/amdgpu: suspend gfx userqueues Shashank Sharma
2024-09-17 11:58 ` Christian König
2024-09-25 9:13 ` Sharma, Shashank
2024-09-09 20:06 ` [PATCH v11 24/28] drm/amdgpu: resume " Shashank Sharma
2024-09-17 12:30 ` Christian König
2024-09-25 9:15 ` Sharma, Shashank
2024-09-09 20:06 ` [PATCH v11 25/28] drm/amdgpu: Add input fence to sync bo unmap Shashank Sharma
2024-09-09 20:06 ` [PATCH v11 26/28] drm/amdgpu: fix MES GFX mask Shashank Sharma
2024-09-17 12:21 ` Christian König
2024-09-09 20:06 ` [PATCH v11 27/28] Revert "drm/amdgpu/gfx11: only enable CP GFX shadowing on SR-IOV" Shashank Sharma
2024-09-09 20:31 ` Alex Deucher
2024-09-11 9:20 ` Sharma, Shashank
2024-09-09 20:06 ` [PATCH v11 28/28] Revert "drm/amdgpu: don't allow userspace to create a doorbell BO" Shashank Sharma
2024-09-17 12:25 ` Christian König
2024-09-19 16:59 ` [PATCH v11 00/28] AMDGPU usermode queues Alex Deucher
2024-09-25 9:14 ` Sharma, Shashank [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=69c5664e-6b70-4f69-98bd-b10403b52691@amd.com \
--to=shashank.sharma@amd.com \
--cc=alexdeucher@gmail.com \
--cc=amd-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox