Re: [PATCH 1/3] drm/amd/display: Add ASICREV_IS_PICASSO

[Harry Wentland <hwentlan-5C7GfCeVMHo@public.gmane.org>]

On 2019-05-14 2:20 p.m., Kazlauskas, Nicholas wrote:
> [CAUTION: External Email]
> 
> On 5/14/19 1:49 PM, Harry Wentland wrote:
>>
>> [WHY]
>> We only want to load DMCU FW on Picasso and Raven 2, not on Raven 1.
>>
>> Signed-off-by: Harry Wentland <harry.wentland@amd.com>
>> ---
>>   drivers/gpu/drm/amd/display/include/dal_asic_id.h | 7 ++++---
>>   1 file changed, 4 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>> index 1a9b7507784f..072d8d7debf5 100644
>> --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>> +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
>> @@ -139,13 +139,14 @@
>>   #define RAVEN1_F0 0xF0
>>   #define RAVEN_UNKNOWN 0xFF
>>
>> -#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> -#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
>> -#endif /* DCN1_01 */
>>   #define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
>>   #define RAVEN1_F0 0xF0
>>   #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
>>
>> +#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
>> +#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
>> +#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
>> +#endif /* DCN1_01 */
> 
> Actually, I just realized a problem with doing this. You'll break builds
> that don't have DCN enabled with the second patch because you're
> guarding these behind the define and the second patch checks
> ASICREV_IS_PICASSO outside of any guard at all.
> 

Whoops. I missed that. The subsequent change ("Drop DCN1_01 guards")
fixes that.

I probably should've ordered these differently.

Harry

> Nicholas Kazlauskas
> 
>>
>>   #define FAMILY_RV 142 /* DCN 1*/
>>
>> --
>> 2.21.0
>>
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> 
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