Re: [PATCH 1/2] Revert "drm/amdgpu/vg20:Restruct uvd.idle_work to support multiple instance (v2)"

["Christian König" <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

Am 17.05.2018 um 19:38 schrieb Alex Deucher:
> This reverts commit 4f7b8507bb4ba19f994e0d72eedd6029961be402.
>
> We don't need separate idle work handles for UVD 7.2.  Both instances are
> driven by the same clock and power.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 17 ++++++++---------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h |  7 +------
>   2 files changed, 9 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index c016c407ab09..0772680371a1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -130,6 +130,8 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>   	unsigned version_major, version_minor, family_id;
>   	int i, j, r;
>   
> +	INIT_DELAYED_WORK(&adev->uvd.inst->idle_work, amdgpu_uvd_idle_work_handler);
> +
>   	switch (adev->asic_type) {
>   #ifdef CONFIG_DRM_AMDGPU_CIK
>   	case CHIP_BONAIRE:
> @@ -236,8 +238,6 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>   		bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
>   
>   	for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
> -		adev->uvd.inst[j].delayed_work.ip_instance = j;
> -		INIT_DELAYED_WORK(&adev->uvd.inst[j].delayed_work.idle_work, amdgpu_uvd_idle_work_handler);
>   
>   		r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
>   					    AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo,
> @@ -318,7 +318,7 @@ int amdgpu_uvd_suspend(struct amdgpu_device *adev)
>   		if (adev->uvd.inst[j].vcpu_bo == NULL)
>   			continue;
>   
> -		cancel_delayed_work_sync(&adev->uvd.inst[j].delayed_work.idle_work);
> +		cancel_delayed_work_sync(&adev->uvd.inst[j].idle_work);
>   
>   		/* only valid for physical mode */
>   		if (adev->asic_type < CHIP_POLARIS10) {
> @@ -1144,10 +1144,9 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
>   
>   static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
>   {
> -	struct amdgpu_delayed_work *my_work = (struct amdgpu_delayed_work *)work;
>   	struct amdgpu_device *adev =
> -		container_of(work, struct amdgpu_device, uvd.inst[my_work->ip_instance].delayed_work.idle_work.work);
> -	unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.inst[my_work->ip_instance].ring);
> +		container_of(work, struct amdgpu_device, uvd.inst->idle_work.work);
> +	unsigned fences = amdgpu_fence_count_emitted(&adev->uvd.inst->ring);
>   
>   	if (fences == 0) {
>   		if (adev->pm.dpm_enabled) {
> @@ -1161,7 +1160,7 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
>   							       AMD_CG_STATE_GATE);
>   		}
>   	} else {
> -		schedule_delayed_work(&adev->uvd.inst[my_work->ip_instance].delayed_work.idle_work, UVD_IDLE_TIMEOUT);
> +		schedule_delayed_work(&adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);
>   	}
>   }
>   
> @@ -1173,7 +1172,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
>   	if (amdgpu_sriov_vf(adev))
>   		return;
>   
> -	set_clocks = !cancel_delayed_work_sync(&adev->uvd.inst[ring->me].delayed_work.idle_work);
> +	set_clocks = !cancel_delayed_work_sync(&adev->uvd.inst->idle_work);
>   	if (set_clocks) {
>   		if (adev->pm.dpm_enabled) {
>   			amdgpu_dpm_enable_uvd(adev, true);
> @@ -1190,7 +1189,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
>   void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring)
>   {
>   	if (!amdgpu_sriov_vf(ring->adev))
> -		schedule_delayed_work(&ring->adev->uvd.inst[ring->me].delayed_work.idle_work, UVD_IDLE_TIMEOUT);
> +		schedule_delayed_work(&ring->adev->uvd.inst->idle_work, UVD_IDLE_TIMEOUT);
>   }
>   
>   /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
> index 7801eb8d4199..b1579fba134c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
> @@ -37,11 +37,6 @@
>   	(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
>   			       8) - AMDGPU_UVD_FIRMWARE_OFFSET)
>   
> -struct amdgpu_delayed_work{
> -	struct delayed_work idle_work;
> -	unsigned ip_instance;
> -};
> -
>   struct amdgpu_uvd_inst {
>   	struct amdgpu_bo	*vcpu_bo;
>   	void			*cpu_addr;
> @@ -49,12 +44,12 @@ struct amdgpu_uvd_inst {
>   	void			*saved_bo;
>   	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];
>   	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];
> +	struct delayed_work	idle_work;
>   	struct amdgpu_ring	ring;
>   	struct amdgpu_ring	ring_enc[AMDGPU_MAX_UVD_ENC_RINGS];
>   	struct amdgpu_irq_src	irq;
>   	struct drm_sched_entity entity;
>   	struct drm_sched_entity entity_enc;
> -	struct amdgpu_delayed_work	delayed_work;
>   	uint32_t                srbm_soft_reset;
>   };
>   

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx