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([2a02:908:1252:fb60:be8a:bd56:1f94:86e7]) by smtp.gmail.com with ESMTPSA id h18sm2993013wru.7.2020.06.02.03.00.33 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Jun 2020 03:00:33 -0700 (PDT) Subject: Re: [PATCH 061/207] drm/amdgpu/mes10.1: implement the ring functions of mes specific To: Alex Deucher , amd-gfx@lists.freedesktop.org References: <20200601180239.1267430-1-alexander.deucher@amd.com> <20200601180239.1267430-58-alexander.deucher@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: <78297506-1670-da85-21d0-b6a32dc945c2@gmail.com> Date: Tue, 2 Jun 2020 12:00:32 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20200601180239.1267430-58-alexander.deucher@amd.com> Content-Language: en-US X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: christian.koenig@amd.com Cc: Alex Deucher , Jack Xiao , Hawking Zhang Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 01.06.20 um 20:00 schrieb Alex Deucher: > From: Jack Xiao > > Implement mes ring functions and set up them. > > Signed-off-by: Jack Xiao > Acked-by: Alex Deucher > Reviewed-by: Hawking Zhang > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 43 ++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > index 4f7e345673ca..80f6812d8ecf 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > @@ -33,6 +33,47 @@ MODULE_FIRMWARE("amdgpu/navi10_mes.bin"); > > #define MES_EOP_SIZE 2048 > > +static void mes_v10_1_ring_set_wptr(struct amdgpu_ring *ring) > +{ > + struct amdgpu_device *adev = ring->adev; > + > + if (ring->use_doorbell) { > + atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], > + ring->wptr); This atomic64_t type case still looks fishy to me. IIRC we agreed to not use them, don't we? > + WDOORBELL64(ring->doorbell_index, ring->wptr); > + } else { > + BUG(); Do we really need the BUG() here and below? Christian. > + } > +} > + > +static u64 mes_v10_1_ring_get_rptr(struct amdgpu_ring *ring) > +{ > + return ring->adev->wb.wb[ring->rptr_offs]; > +} > + > +static u64 mes_v10_1_ring_get_wptr(struct amdgpu_ring *ring) > +{ > + u64 wptr; > + > + if (ring->use_doorbell) > + wptr = atomic64_read((atomic64_t *) > + &ring->adev->wb.wb[ring->wptr_offs]); > + else > + BUG(); > + return wptr; > +} > + > +static const struct amdgpu_ring_funcs mes_v10_1_ring_funcs = { > + .type = AMDGPU_RING_TYPE_MES, > + .align_mask = 1, > + .nop = 0, > + .support_64bit_ptrs = true, > + .get_rptr = mes_v10_1_ring_get_rptr, > + .get_wptr = mes_v10_1_ring_get_wptr, > + .set_wptr = mes_v10_1_ring_set_wptr, > + .insert_nop = amdgpu_ring_insert_nop, > +}; > + > static int mes_v10_1_add_hw_queue(struct amdgpu_mes *mes, > struct mes_add_queue_input *input) > { > @@ -315,6 +356,8 @@ static int mes_v10_1_ring_init(struct amdgpu_device *adev) > > ring = &adev->mes.ring; > > + ring->funcs = &mes_v10_1_ring_funcs; > + > ring->me = 3; > ring->pipe = 0; > ring->queue = 0; _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx