From: "Limonciello, Mario" <mario.limonciello@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>, Huang Rui <ray.huang@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amdgpu/pm: drop pp_power_profile_mode support for APUs
Date: Thu, 28 Oct 2021 22:18:42 -0500 [thread overview]
Message-ID: <7c10a524-db12-4245-333f-3bc9141dda42@amd.com> (raw)
In-Reply-To: <CADnq5_Oq_foFBO3fDCa=Zij53J_ULp=brHkMOm6h_9j0ow1J8w@mail.gmail.com>
On 10/28/2021 22:08, Alex Deucher wrote:
> On Thu, Oct 28, 2021 at 10:35 PM Huang Rui <ray.huang@amd.com> wrote:
>>
>> On Thu, Oct 28, 2021 at 10:53:36AM -0500, Mario Limonciello wrote:
>>> Although this has been plumbed for Renoir, Green Sardine, Van Gogh,
>>> and Yellow Carp the functionality in the SMU doesn't do anything for
>>
>> I double confirmed them in the firmware. These messages are actually
>> existed in SMU firmware of Renoir, Van Gogh, and Green Sardine, we should
>> not remove them in these platforms.
>
> I heard that at least on renoir variants, the messages still exist,
> but they no longer do anything. >
> Alex
>
>
>>
>> And for Yellow Carp, it is better to use a firmware check to skip the
>> function than remove them entirely in case somebody doesn't upgrade his/her
>> SBIOS.
For YC even on older SBIOS the function is a no-op and doesn't "do
anything" from my understanding.
>>
>> Thanks,
>> Ray
>>
>>> these APUs. Drop the associated code with them.
>>>
>>> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
>>> ---
>>> .../gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h | 4 +-
>>> .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 86 ------------------
>>> .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 87 -------------------
>>> .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c | 87 -------------------
>>> 4 files changed, 2 insertions(+), 262 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
>>> index 1d3447991d0c..23d24173bc5d 100644
>>> --- a/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
>>> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v13_0_1_ppsmc.h
>>> @@ -51,7 +51,7 @@
>>> #define PPSMC_MSG_PowerUpVcn 0x07 ///< Power up VCN; VCN is power gated by default
>>> #define PPSMC_MSG_SetHardMinVcn 0x08 ///< For wireless display
>>> #define PPSMC_MSG_SetSoftMinGfxclk 0x09 ///< Set SoftMin for GFXCLK, argument is frequency in MHz
>>> -#define PPSMC_MSG_ActiveProcessNotify 0x0A ///< Set active work load type
>>> +#define PPSMC_MSG_SPARE0 0x0A ///< Spare
>>> #define PPSMC_MSG_ForcePowerDownGfx 0x0B ///< Force power down GFX, i.e. enter GFXOFF
>>> #define PPSMC_MSG_PrepareMp1ForUnload 0x0C ///< Prepare PMFW for GFX driver unload
>>> #define PPSMC_MSG_SetDriverDramAddrHigh 0x0D ///< Set high 32 bits of DRAM address for Driver table transfer
>>> @@ -63,7 +63,7 @@
>>> #define PPSMC_MSG_SetHardMinSocclkByFreq 0x13 ///< Set hard min for SOC CLK
>>> #define PPSMC_MSG_SetSoftMinFclk 0x14 ///< Set hard min for FCLK
>>> #define PPSMC_MSG_SetSoftMinVcn 0x15 ///< Set soft min for VCN clocks (VCLK and DCLK)
>>> -#define PPSMC_MSG_SPARE0 0x16 ///< Spared
>>> +#define PPSMC_MSG_SPARE1 0x16 ///< Spare
>>> #define PPSMC_MSG_GetGfxclkFrequency 0x17 ///< Get GFX clock frequency
>>> #define PPSMC_MSG_GetFclkFrequency 0x18 ///< Get FCLK frequency
>>> #define PPSMC_MSG_AllowGfxOff 0x19 ///< Inform PMFW of allowing GFXOFF entry
>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
>>> index 421f38e8dada..2451d990d577 100644
>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
>>> @@ -72,7 +72,6 @@ static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
>>> MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0),
>>> MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
>>> MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
>>> - MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
>>> MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
>>> MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
>>> MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
>>> @@ -182,14 +181,6 @@ static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
>>> TAB_MAP_VALID(DPMCLOCKS),
>>> };
>>>
>>> -static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
>>> -};
>>> -
>>> static const uint8_t vangogh_throttler_map[] = {
>>> [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
>>> [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
>>> @@ -1010,80 +1001,6 @@ static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
>>> return ret;
>>> }
>>>
>>> -static int vangogh_get_power_profile_mode(struct smu_context *smu,
>>> - char *buf)
>>> -{
>>> - static const char *profile_name[] = {
>>> - "BOOTUP_DEFAULT",
>>> - "3D_FULL_SCREEN",
>>> - "POWER_SAVING",
>>> - "VIDEO",
>>> - "VR",
>>> - "COMPUTE",
>>> - "CUSTOM"};
>>> - uint32_t i, size = 0;
>>> - int16_t workload_type = 0;
>>> -
>>> - if (!buf)
>>> - return -EINVAL;
>>> -
>>> - for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
>>> - /*
>>> - * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
>>> - * Not all profile modes are supported on vangogh.
>>> - */
>>> - workload_type = smu_cmn_to_asic_specific_index(smu,
>>> - CMN2ASIC_MAPPING_WORKLOAD,
>>> - i);
>>> -
>>> - if (workload_type < 0)
>>> - continue;
>>> -
>>> - size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
>>> - i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
>>> - }
>>> -
>>> - return size;
>>> -}
>>> -
>>> -static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
>>> -{
>>> - int workload_type, ret;
>>> - uint32_t profile_mode = input[size];
>>> -
>>> - if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
>>> - dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
>>> - return -EINVAL;
>>> - }
>>> -
>>> - if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
>>> - profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
>>> - return 0;
>>> -
>>> - /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
>>> - workload_type = smu_cmn_to_asic_specific_index(smu,
>>> - CMN2ASIC_MAPPING_WORKLOAD,
>>> - profile_mode);
>>> - if (workload_type < 0) {
>>> - dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
>>> - profile_mode);
>>> - return -EINVAL;
>>> - }
>>> -
>>> - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
>>> - 1 << workload_type,
>>> - NULL);
>>> - if (ret) {
>>> - dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
>>> - workload_type);
>>> - return ret;
>>> - }
>>> -
>>> - smu->power_profile_mode = profile_mode;
>>> -
>>> - return 0;
>>> -}
>>> -
>>> static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
>>> enum smu_clk_type clk_type,
>>> uint32_t min,
>>> @@ -2190,8 +2107,6 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
>>> .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
>>> .system_features_control = vangogh_system_features_control,
>>> .feature_is_enabled = smu_cmn_feature_is_enabled,
>>> - .set_power_profile_mode = vangogh_set_power_profile_mode,
>>> - .get_power_profile_mode = vangogh_get_power_profile_mode,
>>> .get_dpm_clock_table = vangogh_get_dpm_clock_table,
>>> .force_clk_levels = vangogh_force_clk_levels,
>>> .set_performance_level = vangogh_set_performance_level,
>>> @@ -2210,6 +2125,5 @@ void vangogh_set_ppt_funcs(struct smu_context *smu)
>>> smu->message_map = vangogh_message_map;
>>> smu->feature_map = vangogh_feature_mask_map;
>>> smu->table_map = vangogh_table_map;
>>> - smu->workload_map = vangogh_workload_map;
>>> smu->is_apu = true;
>>> }
>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
>>> index 145f13b8c977..21da7989f1ba 100644
>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
>>> @@ -58,7 +58,6 @@ static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
>>> MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
>>> MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1),
>>> MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
>>> - MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
>>> MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1),
>>> MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1),
>>> MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1),
>>> @@ -120,14 +119,6 @@ static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
>>> TAB_MAP_VALID(SMU_METRICS),
>>> };
>>>
>>> -static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
>>> -};
>>> -
>>> static const uint8_t renoir_throttler_map[] = {
>>> [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
>>> [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
>>> @@ -854,46 +845,6 @@ static int renoir_force_clk_levels(struct smu_context *smu,
>>> return ret;
>>> }
>>>
>>> -static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
>>> -{
>>> - int workload_type, ret;
>>> - uint32_t profile_mode = input[size];
>>> -
>>> - if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
>>> - dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
>>> - return -EINVAL;
>>> - }
>>> -
>>> - if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
>>> - profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
>>> - return 0;
>>> -
>>> - /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
>>> - workload_type = smu_cmn_to_asic_specific_index(smu,
>>> - CMN2ASIC_MAPPING_WORKLOAD,
>>> - profile_mode);
>>> - if (workload_type < 0) {
>>> - /*
>>> - * TODO: If some case need switch to powersave/default power mode
>>> - * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving.
>>> - */
>>> - dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
>>> - return -EINVAL;
>>> - }
>>> -
>>> - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
>>> - 1 << workload_type,
>>> - NULL);
>>> - if (ret) {
>>> - dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
>>> - return ret;
>>> - }
>>> -
>>> - smu->power_profile_mode = profile_mode;
>>> -
>>> - return 0;
>>> -}
>>> -
>>> static int renoir_set_peak_clock_by_device(struct smu_context *smu)
>>> {
>>> int ret = 0;
>>> @@ -1092,41 +1043,6 @@ static int renoir_set_watermarks_table(
>>> return 0;
>>> }
>>>
>>> -static int renoir_get_power_profile_mode(struct smu_context *smu,
>>> - char *buf)
>>> -{
>>> - static const char *profile_name[] = {
>>> - "BOOTUP_DEFAULT",
>>> - "3D_FULL_SCREEN",
>>> - "POWER_SAVING",
>>> - "VIDEO",
>>> - "VR",
>>> - "COMPUTE",
>>> - "CUSTOM"};
>>> - uint32_t i, size = 0;
>>> - int16_t workload_type = 0;
>>> -
>>> - if (!buf)
>>> - return -EINVAL;
>>> -
>>> - for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
>>> - /*
>>> - * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
>>> - * Not all profile modes are supported on arcturus.
>>> - */
>>> - workload_type = smu_cmn_to_asic_specific_index(smu,
>>> - CMN2ASIC_MAPPING_WORKLOAD,
>>> - i);
>>> - if (workload_type < 0)
>>> - continue;
>>> -
>>> - size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
>>> - i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
>>> - }
>>> -
>>> - return size;
>>> -}
>>> -
>>> static int renoir_get_smu_metrics_data(struct smu_context *smu,
>>> MetricsMember_t member,
>>> uint32_t *value)
>>> @@ -1389,11 +1305,9 @@ static const struct pptable_funcs renoir_ppt_funcs = {
>>> .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
>>> .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
>>> .force_clk_levels = renoir_force_clk_levels,
>>> - .set_power_profile_mode = renoir_set_power_profile_mode,
>>> .set_performance_level = renoir_set_performance_level,
>>> .get_dpm_clock_table = renoir_get_dpm_clock_table,
>>> .set_watermarks_table = renoir_set_watermarks_table,
>>> - .get_power_profile_mode = renoir_get_power_profile_mode,
>>> .read_sensor = renoir_read_sensor,
>>> .check_fw_status = smu_v12_0_check_fw_status,
>>> .check_fw_version = smu_v12_0_check_fw_version,
>>> @@ -1429,7 +1343,6 @@ void renoir_set_ppt_funcs(struct smu_context *smu)
>>> smu->message_map = renoir_message_map;
>>> smu->clock_map = renoir_clk_map;
>>> smu->table_map = renoir_table_map;
>>> - smu->workload_map = renoir_workload_map;
>>> smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
>>> smu->is_apu = true;
>>> }
>>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
>>> index a403657151ba..8215bbf5ed7c 100644
>>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
>>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c
>>> @@ -64,7 +64,6 @@ static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] =
>>> MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
>>> MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
>>> MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
>>> - MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
>>> MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
>>> MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
>>> MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
>>> @@ -135,14 +134,6 @@ static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = {
>>> TAB_MAP_VALID(CUSTOM_DPM),
>>> TAB_MAP_VALID(DPMCLOCKS),
>>> };
>>> -
>>> -static struct cmn2asic_mapping yellow_carp_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
>>> - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
>>> -};
>>>
>>> static int yellow_carp_init_smc_tables(struct smu_context *smu)
>>> {
>>> @@ -543,81 +534,6 @@ static int yellow_carp_set_watermarks_table(struct smu_context *smu,
>>> return 0;
>>> }
>>>
>>> -static int yellow_carp_get_power_profile_mode(struct smu_context *smu,
>>> - char *buf)
>>> -{
>>> - static const char *profile_name[] = {
>>> - "BOOTUP_DEFAULT",
>>> - "3D_FULL_SCREEN",
>>> - "POWER_SAVING",
>>> - "VIDEO",
>>> - "VR",
>>> - "COMPUTE",
>>> - "CUSTOM"};
>>> - uint32_t i, size = 0;
>>> - int16_t workload_type = 0;
>>> -
>>> - if (!buf)
>>> - return -EINVAL;
>>> -
>>> - for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
>>> - /*
>>> - * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT.
>>> - * Not all profile modes are supported on yellow carp.
>>> - */
>>> - workload_type = smu_cmn_to_asic_specific_index(smu,
>>> - CMN2ASIC_MAPPING_WORKLOAD,
>>> - i);
>>> -
>>> - if (workload_type < 0)
>>> - continue;
>>> -
>>> - size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
>>> - i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
>>> - }
>>> -
>>> - return size;
>>> -}
>>> -
>>> -static int yellow_carp_set_power_profile_mode(struct smu_context *smu,
>>> - long *input, uint32_t size)
>>> -{
>>> - int workload_type, ret;
>>> - uint32_t profile_mode = input[size];
>>> -
>>> - if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
>>> - dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
>>> - return -EINVAL;
>>> - }
>>> -
>>> - if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
>>> - profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
>>> - return 0;
>>> -
>>> - /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
>>> - workload_type = smu_cmn_to_asic_specific_index(smu,
>>> - CMN2ASIC_MAPPING_WORKLOAD,
>>> - profile_mode);
>>> - if (workload_type < 0) {
>>> - dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on YELLOWCARP\n",
>>> - profile_mode);
>>> - return -EINVAL;
>>> - }
>>> -
>>> - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
>>> - 1 << workload_type,
>>> - NULL);
>>> - if (ret) {
>>> - dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
>>> - workload_type);
>>> - return ret;
>>> - }
>>> -
>>> - smu->power_profile_mode = profile_mode;
>>> -
>>> - return 0;
>>> -}
>>> -
>>> static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
>>> void **table)
>>> {
>>> @@ -1238,8 +1154,6 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = {
>>> .read_sensor = yellow_carp_read_sensor,
>>> .is_dpm_running = yellow_carp_is_dpm_running,
>>> .set_watermarks_table = yellow_carp_set_watermarks_table,
>>> - .get_power_profile_mode = yellow_carp_get_power_profile_mode,
>>> - .set_power_profile_mode = yellow_carp_set_power_profile_mode,
>>> .get_gpu_metrics = yellow_carp_get_gpu_metrics,
>>> .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
>>> .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
>>> @@ -1261,6 +1175,5 @@ void yellow_carp_set_ppt_funcs(struct smu_context *smu)
>>> smu->message_map = yellow_carp_message_map;
>>> smu->feature_map = yellow_carp_feature_mask_map;
>>> smu->table_map = yellow_carp_table_map;
>>> - smu->workload_map = yellow_carp_workload_map;
>>> smu->is_apu = true;
>>> }
>>> --
>>> 2.25.1
>>>
prev parent reply other threads:[~2021-10-29 3:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-28 15:53 [PATCH] drm/amdgpu/pm: drop pp_power_profile_mode support for APUs Mario Limonciello
2021-10-29 2:03 ` Liu, Aaron
2021-10-29 2:22 ` Liu, Aaron
2021-10-29 2:35 ` Huang Rui
2021-10-29 3:08 ` Alex Deucher
2021-10-29 3:18 ` Limonciello, Mario [this message]
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