AMD-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Christian König" <christian.koenig@amd.com>
To: "Paneer Selvam, Arunpravin" <arunpravin.paneerselvam@amd.com>,
	"Christian König" <ckoenig.leichtzumerken@gmail.com>,
	amd-gfx@lists.freedesktop.org
Cc: alexander.deucher@amd.com
Subject: Re: [PATCH v2 01/08] drm/amdgpu: Implement userqueue signal/wait IOCTL
Date: Thu, 26 Sep 2024 13:16:45 +0200	[thread overview]
Message-ID: <7e28bb62-a72e-4e5b-a035-fcecc94033e9@amd.com> (raw)
In-Reply-To: <e37ec78b-2d1d-4cc6-8b3f-4e9e391275b8@amd.com>

Am 26.09.24 um 12:26 schrieb Paneer Selvam, Arunpravin:
> Hi Christian,
>
> On 9/26/2024 3:04 PM, Christian König wrote:
>> Am 26.09.24 um 11:31 schrieb Paneer Selvam, Arunpravin:
>>> Hi Christian,
>>>
>>> On 9/26/2024 2:57 PM, Christian König wrote:
>>>> Am 25.09.24 um 21:59 schrieb Arunpravin Paneer Selvam:
>>>>> [SNIP]
>>>>> +int amdgpu_userq_wait_ioctl(struct drm_device *dev, void *data,
>>>>> +                struct drm_file *filp)
>>>>> +{
>>>>> +    struct drm_amdgpu_userq_fence_info *fence_info = NULL;
>>>>> +    struct drm_amdgpu_userq_wait *wait_info = data;
>>>>> +    u32 *syncobj_handles, *bo_handles;
>>>>> +    struct dma_fence **fences = NULL;
>>>>> +    u32 num_syncobj, num_bo_handles;
>>>>> +    struct drm_gem_object **gobj;
>>>>> +    struct drm_exec exec;
>>>>> +    int r, i, entry, cnt;
>>>>> +    u64 num_fences = 0;
>>>>> +
>>>>> +    num_bo_handles = wait_info->num_bo_handles;
>>>>> +    bo_handles = 
>>>>> memdup_user(u64_to_user_ptr(wait_info->bo_handles_array),
>>>>> +                 sizeof(u32) * num_bo_handles);
>>>>> +    if (IS_ERR(bo_handles))
>>>>> +        return PTR_ERR(bo_handles);
>>>>> +
>>>>> +    num_syncobj = wait_info->num_syncobj_handles;
>>>>> +    syncobj_handles = 
>>>>> memdup_user(u64_to_user_ptr(wait_info->syncobj_handles_array),
>>>>> +                      sizeof(u32) * num_syncobj);
>>>>> +    if (IS_ERR(syncobj_handles)) {
>>>>> +        r = PTR_ERR(syncobj_handles);
>>>>> +        goto free_bo_handles;
>>>>> +    }
>>>>> +
>>>>> +    /* Array of GEM object handles */
>>>>> +    gobj = kmalloc_array(num_bo_handles, sizeof(*gobj), GFP_KERNEL);
>>>>> +    if (!gobj) {
>>>>> +        r = -ENOMEM;
>>>>> +        goto free_syncobj_handles;
>>>>> +    }
>>>>> +
>>>>> +    for (entry = 0; entry < num_bo_handles; entry++) {
>>>>> +        gobj[entry] = drm_gem_object_lookup(filp, 
>>>>> bo_handles[entry]);
>>>>> +        if (!gobj[entry]) {
>>>>> +            r = -ENOENT;
>>>>> +            goto put_gobj;
>>>>> +        }
>>>>> +    }
>>>>> +
>>>>> +    drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT, 0);
>>>>> +    drm_exec_until_all_locked(&exec) {
>>>>> +        r = drm_exec_prepare_array(&exec, gobj, num_bo_handles, 0);
>>>>> +        drm_exec_retry_on_contention(&exec);
>>>>> +        if (r) {
>>>>> +            drm_exec_fini(&exec);
>>>>> +            goto put_gobj;
>>>>> +        }
>>>>> +    }
>>>>> +
>>>>> +    if (!wait_info->num_fences) {
>>>>> +        /* Count syncobj's fence */
>>>>> +        for (i = 0; i < num_syncobj; i++) {
>>>>> +            struct dma_fence *fence;
>>>>> +
>>>>> +            r = drm_syncobj_find_fence(filp, syncobj_handles[i],
>>>>> +                           0, 0, &fence);
>>>>> +            dma_fence_put(fence);
>>>>> +
>>>>> +            if (r || !fence)
>>>>> +                continue;
>>>>> +
>>>>> +            num_fences++;
>>>>> +        }
>>>>> +
>>>>> +        /* Count GEM objects fence */
>>>>> +        for (i = 0; i < num_bo_handles; i++) {
>>>>> +            struct dma_resv_iter resv_cursor;
>>>>> +            struct dma_fence *fence;
>>>>> +
>>>>> +            dma_resv_for_each_fence(&resv_cursor, gobj[i]->resv,
>>>>> + dma_resv_usage_rw(wait_info->bo_wait_flags &
>>>>> +                        AMDGPU_USERQ_BO_WRITE), fence)
>>>>> +                num_fences++;
>>>>
>>>> We should probably adjust the UAPI here once more.
>>>>
>>>> The problem is that we only provide the AMDGPU_USERQ_BO_WRITE for 
>>>> the whole IOCTL instead of per BO.
>>>>
>>>> So the best approach would probably be to drop the 
>>>> AMDGPU_USERQ_BO_WRITE flag and split up the array of BOs into 
>>>> readers and writers.
>>>>
>>>> Can you work on that Arun? Shouldn't be more than a bit typing 
>>>> exercise.
>>> Sure, I will modify and send the next version of this file.
>>
>> Thanks.
>>
>> In the meantime I'm going to review the rest of the series, so there 
>> could be more comments. But please update the UAPI first.
>
> Can we have the bo_handles_read_array, num_read_bo_handles, 
> bo_handles_write_array, num_write_bo_handles in both
> signal IOCTL and wait IOCTL?

I think so, yes.

Regards,
Christian.

>
> Thanks,
> Arun.
>>
>> Regards,
>> Christian.
>>
>>>
>>> Thanks,
>>> Arun.
>>>>
>>>> Thanks,
>>>> Christian.
>>>>
>>>
>>
>


      reply	other threads:[~2024-09-26 11:16 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-25 19:59 [PATCH v2 01/08] drm/amdgpu: Implement userqueue signal/wait IOCTL Arunpravin Paneer Selvam
2024-09-25 19:59 ` [PATCH v2 02/08] drm/amdgpu: screen freeze and userq driver crash Arunpravin Paneer Selvam
2024-09-26 11:38   ` Christian König
2024-09-25 19:59 ` [PATCH v2 03/08] drm/amdgpu: Add wait IOCTL timeline syncobj support Arunpravin Paneer Selvam
2024-09-26 11:49   ` Christian König
2024-09-25 19:59 ` [PATCH v2 04/08] drm/amdgpu: Enable userq fence interrupt support Arunpravin Paneer Selvam
2024-09-25 19:59 ` [PATCH v2 05/08] drm/amdgpu: Remove the MES self test Arunpravin Paneer Selvam
2024-09-25 19:59 ` [PATCH v2 06/08] drm/amdgpu: Add few optimizations to userq fence driver Arunpravin Paneer Selvam
2024-09-26 12:28   ` Christian König
2024-09-25 19:59 ` [PATCH v2 07/08] drm/amdgpu: Add the missing error handling for xa_store() call Arunpravin Paneer Selvam
2024-09-26 12:29   ` Christian König
2024-09-25 19:59 ` [PATCH v2 08/08] drm/amdgpu: add vm root BO lock before accessing the vm Arunpravin Paneer Selvam
2024-09-26 12:32   ` Christian König
2024-09-26  9:27 ` [PATCH v2 01/08] drm/amdgpu: Implement userqueue signal/wait IOCTL Christian König
2024-09-26  9:31   ` Paneer Selvam, Arunpravin
2024-09-26  9:34     ` Christian König
2024-09-26 10:26       ` Paneer Selvam, Arunpravin
2024-09-26 11:16         ` Christian König [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=7e28bb62-a72e-4e5b-a035-fcecc94033e9@amd.com \
    --to=christian.koenig@amd.com \
    --cc=alexander.deucher@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=arunpravin.paneerselvam@amd.com \
    --cc=ckoenig.leichtzumerken@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox