From: "Lazar, Lijo" <lijo.lazar@amd.com>
To: sguttula <suresh.guttula@amd.com>,
Alexander.Deucher@amd.com, amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailbox
Date: Thu, 26 Feb 2026 19:38:33 +0530 [thread overview]
Message-ID: <80fd61ee-becd-4b92-a592-8f7a1a9f960e@amd.com> (raw)
In-Reply-To: <20260226105757.883463-1-suresh.guttula@amd.com>
On 26-Feb-26 4:27 PM, sguttula wrote:
> The reason the RAP is not granting access to 0x58200 is that
> a dedicated RSMU slot would have to be spent for this address range,
> and MPASP is close to running out of RSMU slots.
>
> This will help to fix PSP TOC load failure during secureboot.
> GFX Driver Need to use indirect access for SMN address regs.
>
> Signed-off-by: sguttula <suresh.guttula@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v15_0.c | 20 +++++++++----------
> .../include/asic_reg/mp/mp_15_0_0_offset.h | 18 +++++++++++++++++
> 2 files changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
> index 723ddae17644..73a709773e85 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0.c
> @@ -69,12 +69,12 @@ static int psp_v15_0_0_ring_stop(struct psp_context *psp,
> 0x80000000, 0x80000000, false);
> } else {
> /* Write the ring destroy command*/
> - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
> + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64,
> GFX_CTRL_CMD_ID_DESTROY_RINGS);
> /* there might be handshake issue with hardware which needs delay */
> mdelay(20);
> /* Wait for response flag (bit 31) */
> - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
> + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
> 0x80000000, 0x80000000, false);
> }
>
> @@ -116,7 +116,7 @@ static int psp_v15_0_0_ring_create(struct psp_context *psp,
>
> } else {
> /* Wait for sOS ready for ring creation */
> - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
> + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
> 0x80000000, 0x80000000, false);
> if (ret) {
> DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
> @@ -125,23 +125,23 @@ static int psp_v15_0_0_ring_create(struct psp_context *psp,
>
> /* Write low address of the ring to C2PMSG_69 */
> psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
> - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
> + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_69, psp_ring_reg);
> /* Write high address of the ring to C2PMSG_70 */
> psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
> - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
> + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_70, psp_ring_reg);
> /* Write size of ring to C2PMSG_71 */
> psp_ring_reg = ring->ring_size;
> - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
> + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_71, psp_ring_reg);
> /* Write the ring initialization command to C2PMSG_64 */
> psp_ring_reg = ring_type;
> psp_ring_reg = psp_ring_reg << 16;
> - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
> + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64, psp_ring_reg);
>
> /* there might be handshake issue with hardware which needs delay */
> mdelay(20);
>
> /* Wait for response flag (bit 31) in C2PMSG_64 */
> - ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
> + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_64),
> 0x80000000, 0x8000FFFF, false);
> }
>
> @@ -174,7 +174,7 @@ static uint32_t psp_v15_0_0_ring_get_wptr(struct psp_context *psp)
> if (amdgpu_sriov_vf(adev))
> data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
> else
> - data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
> + data = RREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67);
>
> return data;
> }
> @@ -188,7 +188,7 @@ static void psp_v15_0_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
> WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
> GFX_CTRL_CMD_ID_CONSUME_CMD);
> } else
> - WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
> + WREG32_SOC15(MP0, 0, regMPASP_PCRU1_MPASP_C2PMSG_67, value);
> }
>
> static const struct psp_funcs psp_v15_0_0_funcs = {
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
> index 0e4c195297a4..fe97943b9b97 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_15_0_0_offset.h
> @@ -82,6 +82,24 @@
> #define regMPASP_SMN_IH_SW_INT_CTRL 0x0142
> #define regMPASP_SMN_IH_SW_INT_CTRL_BASE_IDX 0
>
> +// addressBlock: mp_SmuMpASPPub_PcruDec
> +// base address: 0x3800000
> +#define regMPASP_PCRU1_MPASP_C2PMSG_64 0x4280
> +#define regMPASP_PCRU1_MPASP_C2PMSG_64_BASE_IDX 3
> +#define regMPASP_PCRU1_MPASP_C2PMSG_65 0x4281
> +#define regMPASP_PCRU1_MPASP_C2PMSG_65_BASE_IDX 3
> +#define regMPASP_PCRU1_MPASP_C2PMSG_66 0x4282
> +#define regMPASP_PCRU1_MPASP_C2PMSG_66_BASE_IDX 3
> +#define regMPASP_PCRU1_MPASP_C2PMSG_67 0x4283
> +#define regMPASP_PCRU1_MPASP_C2PMSG_67_BASE_IDX 3
> +#define regMPASP_PCRU1_MPASP_C2PMSG_68 0x4284
> +#define regMPASP_PCRU1_MPASP_C2PMSG_68_BASE_IDX 3
> +#define regMPASP_PCRU1_MPASP_C2PMSG_69 0x4285
> +#define regMPASP_PCRU1_MPASP_C2PMSG_69_BASE_IDX 3
> +#define regMPASP_PCRU1_MPASP_C2PMSG_70 0x4286
> +#define regMPASP_PCRU1_MPASP_C2PMSG_70_BASE_IDX 3
> +#define regMPASP_PCRU1_MPASP_C2PMSG_71 0x4287
> +#define regMPASP_PCRU1_MPASP_C2PMSG_71_BASE_IDX 3
>
> // addressBlock: mp_SmuMp1_SmnDec
> // base address: 0x0
prev parent reply other threads:[~2026-02-26 14:09 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-26 10:57 [PATCH] drm/amdgpu/psp: Use Indirect access address for GFX to PSP mailbox sguttula
2026-02-26 14:08 ` Lazar, Lijo [this message]
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