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From: "Christian König" <ckoenig.leichtzumerken@gmail.com>
To: Felix Kuehling <felix.kuehling@amd.com>,
	Alex Deucher <alexdeucher@gmail.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/3] drm/amdgpu: enabled software IH ring for Vega
Date: Mon, 2 Nov 2020 20:58:08 +0100	[thread overview]
Message-ID: <87eea327-ede5-054b-e8da-c8b5c7ba11e9@gmail.com> (raw)
In-Reply-To: <29159f4d-e769-193c-b304-d21693519be1@amd.com>

Am 02.11.20 um 19:59 schrieb Felix Kuehling:
> Am 2020-11-02 um 1:53 p.m. schrieb Alex Deucher:
>> On Mon, Nov 2, 2020 at 6:34 AM Christian König
>> <ckoenig.leichtzumerken@gmail.com> wrote:
>>> Seems like we won't get the hardware IH1/2 rings on Vega20 working.
>>>
>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 7 +++++++
>>>   1 file changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>> index 407c6093c2ec..cef61dd46a37 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>> @@ -91,6 +91,9 @@ static void vega10_ih_enable_interrupts(struct amdgpu_device *adev)
>>>                  }
>>>                  adev->irq.ih2.enabled = true;
>>>          }
>>> +
>>> +       if (adev->irq.ih_soft.ring_size)
>>> +               adev->irq.ih_soft.enabled = true;
>>>   }
>>>
>>>   /**
>>> @@ -606,6 +609,10 @@ static int vega10_ih_sw_init(void *handle)
>>>          adev->irq.ih2.use_doorbell = true;
>>>          adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
>>>
>>> +       r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
>>> +       if (r)
>>> +               return r;
>>> +
>> Should we only enable this on vega20?
> It affects other GPUs as well. Including probably some Navi GPUs. We'll
> probably need a similar change in navi10_ih.c.
>
> Is there a way to reliably detect whether IH redirection works. Or do we
> need to allocate the soft IH ring unconditionally?

We can allocate it unconditionally on Vega and Navi, it's just a single 
page ring buffer which is only used when needed.

What worries me more is that testing shows that I can't even enable IV 
tracing or risk that a single CPU becomes so busy with processing IVs 
that I get "stuck for 23 seconds" warnings.

We *really* need the hardware to work correctly either by using the CAM 
for filtering page faults or by redirecting them to the different IH ring.

Regards,
Christian.

>
> Regards,
>    Felix
>
>
>> Alex
>>
>>
>>>          r = amdgpu_irq_init(adev);
>>>
>>>          return r;
>>> --
>>> 2.25.1
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

_______________________________________________
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  reply	other threads:[~2020-11-02 19:58 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-02 11:33 [PATCH 1/3] drm/amdgpu: add infrastructure for soft IH ring Christian König
2020-11-02 11:33 ` [PATCH 2/3] drm/amdgpu: enabled software IH ring for Vega Christian König
2020-11-02 18:53   ` Alex Deucher
2020-11-02 18:59     ` Felix Kuehling
2020-11-02 19:58       ` Christian König [this message]
2020-11-03 13:26         ` Christian König
2020-11-02 11:33 ` [PATCH 3/3] drm/amdgpu: make sure retry faults are handled in a work item on Vega Christian König

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