From: "Lazar, Lijo" <lijo.lazar@amd.com>
To: Asad Kamal <asad.kamal@amd.com>, amd-gfx@lists.freedesktop.org
Cc: hawking.zhang@amd.com, le.ma@amd.com, shiwu.zhang@amd.com,
alexander.deucher@amd.com, KevinYang.Wang@amd.com
Subject: Re: [PATCH v2 2/4] drm/amd/pm: Add ppt1 support for smu_v13_0_12
Date: Thu, 6 Nov 2025 18:55:18 +0530 [thread overview]
Message-ID: <8fbf5ceb-460c-4b32-b68f-6654717c3adf@amd.com> (raw)
In-Reply-To: <20251106114421.3770378-2-asad.kamal@amd.com>
On 11/6/2025 5:14 PM, Asad Kamal wrote:
> Add support to configure and retrieve ppt1 limit for smu_v13_0_12
>
> v2: Add update_caps function and update ppt1 cap based on max ppt1
> value, optimize the return values (Lijo)
>
> Signed-off-by: Asad Kamal <asad.kamal@amd.com>
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 4 +-
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 8 ++
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 79 ++++++++++++++++++-
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 4 +
> 4 files changed, 91 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> index 2256c77da636..5fb71d4398f4 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
> @@ -279,7 +279,9 @@
> __SMU_DUMMY_MAP(ResetSDMA), \
> __SMU_DUMMY_MAP(ResetVCN), \
> __SMU_DUMMY_MAP(GetStaticMetricsTable), \
> - __SMU_DUMMY_MAP(GetSystemMetricsTable),
> + __SMU_DUMMY_MAP(GetSystemMetricsTable), \
> + __SMU_DUMMY_MAP(SetFastPptLimit), \
> + __SMU_DUMMY_MAP(GetFastPptLimit),
>
> #undef __SMU_DUMMY_MAP
> #define __SMU_DUMMY_MAP(type) SMU_MSG_##type
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
> index a0c844bf852c..e2851b26593a 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
> @@ -139,6 +139,8 @@ const struct cmn2asic_msg_mapping smu_v13_0_12_message_map[SMU_MSG_MAX_COUNT] =
> MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0),
> MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1),
> MSG_MAP(GetSystemMetricsTable, PPSMC_MSG_GetSystemMetricsTable, 1),
> + MSG_MAP(SetFastPptLimit, PPSMC_MSG_SetFastPptLimit, 1),
> + MSG_MAP(GetFastPptLimit, PPSMC_MSG_GetFastPptLimit, 1),
> };
>
> int smu_v13_0_12_tables_init(struct smu_context *smu)
> @@ -345,6 +347,12 @@ int smu_v13_0_12_setup_driver_pptable(struct smu_context *smu)
> if (smu_v13_0_6_cap_supported(smu, SMU_CAP(NPM_METRICS)))
> pptable->MaxNodePowerLimit =
> SMUQ10_ROUND(static_metrics->MaxNodePowerLimit);
> + if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) &&
> + static_metrics->PPT1Max) {
> + pptable->PPT1Max = static_metrics->PPT1Max;
> + pptable->PPT1Min = static_metrics->PPT1Min;
> + pptable->PPT1Default = static_metrics->PPT1Default;
> + }
> smu_v13_0_12_init_xgmi_data(smu, static_metrics);
> pptable->Init = true;
> }
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> index 197fd91e1fb4..282bd00a909c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> @@ -851,6 +851,17 @@ int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu)
> return 0;
> }
>
> +static void smu_v13_0_6_update_caps(struct smu_context *smu)
> +{
> + struct smu_table_context *smu_table = &smu->smu_table;
> + struct PPTable_t *pptable =
> + (struct PPTable_t *)smu_table->driver_pptable;
> +
> + if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) &&
> + !pptable->PPT1Max)
> + smu_v13_0_6_cap_clear(smu, SMU_CAP(FAST_PPT));
> +}
> +
> static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
> {
> struct smu_table_context *smu_table = &smu->smu_table;
> @@ -867,8 +878,12 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
> uint8_t max_width;
>
> if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
> - smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
> - return smu_v13_0_12_setup_driver_pptable(smu);
> + smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
> + ret = smu_v13_0_12_setup_driver_pptable(smu);
> + if (ret)
> + return ret;
> + goto out;
> + }
>
> /* Store one-time values in driver PPTable */
> if (!pptable->Init) {
> @@ -948,7 +963,8 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
> smu_v13_0_6_fill_static_metrics_table(smu, static_metrics);
> }
> }
> -
> +out:
> + smu_v13_0_6_update_caps(smu);
> return 0;
> }
>
> @@ -1882,9 +1898,65 @@ static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
> enum smu_ppt_limit_type limit_type,
> uint32_t limit)
> {
> + struct smu_table_context *smu_table = &smu->smu_table;
> + struct PPTable_t *pptable =
> + (struct PPTable_t *)smu_table->driver_pptable;
> + int ret;
> +
> + if (limit_type == SMU_FAST_PPT_LIMIT) {
> + if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)))
> + return -EOPNOTSUPP;
> + if (limit > pptable->PPT1Max || limit < pptable->PPT1Min) {
> + dev_err(smu->adev->dev,
> + "New power limit (%d) should be between min %d max %d\n",
> + limit, pptable->PPT1Min, pptable->PPT1Max);
> + return -EINVAL;
> + }
> + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetFastPptLimit,
> + limit, NULL);
> + if (ret)
> + dev_err(smu->adev->dev, "Set fast PPT limit failed!\n");
> + return ret;
> + }
> +
> return smu_v13_0_set_power_limit(smu, limit_type, limit);
> }
>
> +static int smu_v13_0_6_get_ppt_limit(struct smu_context *smu,
> + uint32_t *ppt_limit,
> + enum smu_ppt_limit_type type,
> + enum smu_ppt_limit_level level)
> +{
> + struct smu_table_context *smu_table = &smu->smu_table;
> + struct PPTable_t *pptable =
> + (struct PPTable_t *)smu_table->driver_pptable;
> + int ret = 0;
> +
> + if (type == SMU_FAST_PPT_LIMIT) {
> + if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)))
> + return -EOPNOTSUPP;
> + switch (level) {
> + case SMU_PPT_LIMIT_MAX:
> + *ppt_limit = pptable->PPT1Max;
> + break;
> + case SMU_PPT_LIMIT_CURRENT:
> + ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPptLimit, ppt_limit);
> + if (ret)
> + dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
> + break;
> + case SMU_PPT_LIMIT_DEFAULT:
> + *ppt_limit = pptable->PPT1Default;
> + break;
> + case SMU_PPT_LIMIT_MIN:
> + *ppt_limit = pptable->PPT1Min;
> + break;
> + default:
> + break;
> + }
> + }
> + return ret;
Since there is an out param, returning success for other limit
types/unrecognized limit levels is not preferred. Better to return as
not supported.
Thanks,
Lijo
> +}
> +
> static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
> struct amdgpu_irq_src *source,
> struct amdgpu_iv_entry *entry)
> @@ -3934,6 +4006,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
> .get_enabled_mask = smu_v13_0_6_get_enabled_mask,
> .feature_is_enabled = smu_cmn_feature_is_enabled,
> .set_power_limit = smu_v13_0_6_set_power_limit,
> + .get_ppt_limit = smu_v13_0_6_get_ppt_limit,
> .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
> .register_irq_handler = smu_v13_0_6_register_irq_handler,
> .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
> index 7ef5f3e66c27..4a47025b49e0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
> @@ -50,6 +50,9 @@ struct PPTable_t {
> uint32_t MinLclkDpmRange;
> uint64_t PublicSerialNumber_AID;
> uint32_t MaxNodePowerLimit;
> + uint32_t PPT1Max;
> + uint32_t PPT1Min;
> + uint32_t PPT1Default;
> bool Init;
> };
>
> @@ -72,6 +75,7 @@ enum smu_v13_0_6_caps {
> SMU_CAP(PLDM_VERSION),
> SMU_CAP(TEMP_METRICS),
> SMU_CAP(NPM_METRICS),
> + SMU_CAP(FAST_PPT),
> SMU_CAP(ALL),
> };
>
next prev parent reply other threads:[~2025-11-06 13:25 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-06 11:44 [PATCH v2 1/4] drm/amd/pm: Update pmfw headers for smuv_13_0_12 Asad Kamal
2025-11-06 11:44 ` [PATCH v2 2/4] drm/amd/pm: Add ppt1 support for smu_v13_0_12 Asad Kamal
2025-11-06 13:25 ` Lazar, Lijo [this message]
2025-11-06 11:44 ` [PATCH v2 3/4] drm/amd/pm: Expose ppt1 limit for gc_v9_5_0 Asad Kamal
2025-11-06 13:28 ` Lazar, Lijo
2025-11-06 11:44 ` [PATCH v2 4/4] drm/amd/pm: Enable ppt1 caps for smu_v13_0_12 Asad Kamal
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