Re: [PATCH] drm/amdkfd: flag per-queue reset support for gfx9

[Harish Kasiviswanathan <harish.kasiviswanathan@amd.com>]

Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>


On 2024-10-22 13:36, Jonathan Kim wrote:
> Flag KFD support for per-queue reset on GFX9 devices.
> 
> Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 ++
>  include/uapi/linux/kfd_sysfs.h            | 3 ++-
>  2 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> index 3871591c9aec..9476e30d6baa 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c
> @@ -1998,6 +1998,8 @@ static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)
>  		if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(9, 4, 2))
>  			dev->node_props.capability |=
>  				HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;
> +
> +		dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED;
>  	} else {
>  		dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
>  					HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
> diff --git a/include/uapi/linux/kfd_sysfs.h b/include/uapi/linux/kfd_sysfs.h
> index 5e8d28617efa..859b8e91d4d3 100644
> --- a/include/uapi/linux/kfd_sysfs.h
> +++ b/include/uapi/linux/kfd_sysfs.h
> @@ -60,7 +60,8 @@
>  #define HSA_CAP_FLAGS_COHERENTHOSTACCESS			0x10000000
>  #define HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED			0x20000000
>  #define HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED	0x40000000
> -#define HSA_CAP_RESERVED					0x800f8000
> +#define HSA_CAP_PER_QUEUE_RESET_SUPPORTED			0x80000000
> +#define HSA_CAP_RESERVED					0x000f8000
>  
>  /* debug_prop bits in node properties */
>  #define HSA_DBG_WATCH_ADDR_MASK_LO_BIT_MASK     0x0000000f