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[165.204.72.6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378e71f068esm7226909f8f.3.2024.09.16.05.39.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Sep 2024 05:39:03 -0700 (PDT) Message-ID: <9c1c606f-5d5b-4dba-9dc7-96a36d2d917f@gmail.com> Date: Mon, 16 Sep 2024 14:39:01 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v11 08/28] drm/amdgpu: map wptr BO into GART To: Shashank Sharma , amd-gfx@lists.freedesktop.org Cc: Alex Deucher , Christian Koenig , Arvind Yadav References: <20240909200614.481-1-shashank.sharma@amd.com> <20240909200614.481-9-shashank.sharma@amd.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <20240909200614.481-9-shashank.sharma@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 09.09.24 um 22:05 schrieb Shashank Sharma: > To support oversubscription, MES FW expects WPTR BOs to > be mapped into GART, before they are submitted to usermode > queues. This patch adds a function for the same. > > V4: fix the wptr value before mapping lookup (Bas, Christian). > > V5: Addressed review comments from Christian: > - Either pin object or allocate from GART, but not both. > - All the handling must be done with the VM locks held. > > V7: Addressed review comments from Christian: > - Do not take vm->eviction_lock > - Use amdgpu_bo_gpu_offset to get the wptr_bo GPU offset > > V8: Rebase > V9: Changed the function names from gfx_v11* to mes_v11* > V10: Remove unused adev (Harish) > > Cc: Alex Deucher > Cc: Christian Koenig > Signed-off-by: Shashank Sharma > Signed-off-by: Arvind Yadav Reviewed-by: Christian König > --- > .../gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c | 76 +++++++++++++++++++ > .../gpu/drm/amd/include/amdgpu_userqueue.h | 1 + > 2 files changed, 77 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c > index a1bc6f488928..90511abaef05 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0_userqueue.c > @@ -30,6 +30,73 @@ > #define AMDGPU_USERQ_PROC_CTX_SZ PAGE_SIZE > #define AMDGPU_USERQ_GANG_CTX_SZ PAGE_SIZE > > +static int > +mes_v11_0_map_gtt_bo_to_gart(struct amdgpu_bo *bo) > +{ > + int ret; > + > + ret = amdgpu_bo_reserve(bo, true); > + if (ret) { > + DRM_ERROR("Failed to reserve bo. ret %d\n", ret); > + goto err_reserve_bo_failed; > + } > + > + ret = amdgpu_ttm_alloc_gart(&bo->tbo); > + if (ret) { > + DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); > + goto err_map_bo_gart_failed; > + } > + > + amdgpu_bo_unreserve(bo); > + bo = amdgpu_bo_ref(bo); > + > + return 0; > + > +err_map_bo_gart_failed: > + amdgpu_bo_unreserve(bo); > +err_reserve_bo_failed: > + return ret; > +} > + > +static int > +mes_v11_0_create_wptr_mapping(struct amdgpu_userq_mgr *uq_mgr, > + struct amdgpu_usermode_queue *queue, > + uint64_t wptr) > +{ > + struct amdgpu_bo_va_mapping *wptr_mapping; > + struct amdgpu_vm *wptr_vm; > + struct amdgpu_userq_obj *wptr_obj = &queue->wptr_obj; > + int ret; > + > + wptr_vm = queue->vm; > + ret = amdgpu_bo_reserve(wptr_vm->root.bo, false); > + if (ret) > + return ret; > + > + wptr &= AMDGPU_GMC_HOLE_MASK; > + wptr_mapping = amdgpu_vm_bo_lookup_mapping(wptr_vm, wptr >> PAGE_SHIFT); > + amdgpu_bo_unreserve(wptr_vm->root.bo); > + if (!wptr_mapping) { > + DRM_ERROR("Failed to lookup wptr bo\n"); > + return -EINVAL; > + } > + > + wptr_obj->obj = wptr_mapping->bo_va->base.bo; > + if (wptr_obj->obj->tbo.base.size > PAGE_SIZE) { > + DRM_ERROR("Requested GART mapping for wptr bo larger than one page\n"); > + return -EINVAL; > + } > + > + ret = mes_v11_0_map_gtt_bo_to_gart(wptr_obj->obj); > + if (ret) { > + DRM_ERROR("Failed to map wptr bo to GART\n"); > + return ret; > + } > + > + queue->wptr_obj.gpu_addr = amdgpu_bo_gpu_offset_no_check(wptr_obj->obj); > + return 0; > +} > + > static int mes_v11_0_userq_map(struct amdgpu_userq_mgr *uq_mgr, > struct amdgpu_usermode_queue *queue, > struct amdgpu_mqd_prop *userq_props) > @@ -61,6 +128,7 @@ static int mes_v11_0_userq_map(struct amdgpu_userq_mgr *uq_mgr, > queue_input.queue_size = userq_props->queue_size >> 2; > queue_input.doorbell_offset = userq_props->doorbell_index; > queue_input.page_table_base_addr = amdgpu_gmc_pd_addr(queue->vm->root.bo); > + queue_input.wptr_mc_addr = queue->wptr_obj.gpu_addr; > > amdgpu_mes_lock(&adev->mes); > r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input); > @@ -168,6 +236,13 @@ static int mes_v11_0_userq_mqd_create(struct amdgpu_userq_mgr *uq_mgr, > goto free_mqd; > } > > + /* FW expects WPTR BOs to be mapped into GART */ > + r = mes_v11_0_create_wptr_mapping(uq_mgr, queue, userq_props->wptr_gpu_addr); > + if (r) { > + DRM_ERROR("Failed to create WPTR mapping\n"); > + goto free_ctx; > + } > + > /* Map userqueue into FW using MES */ > r = mes_v11_0_userq_map(uq_mgr, queue, userq_props); > if (r) { > @@ -194,6 +269,7 @@ mes_v11_0_userq_mqd_destroy(struct amdgpu_userq_mgr *uq_mgr, > struct amdgpu_usermode_queue *queue) > { > mes_v11_0_userq_unmap(uq_mgr, queue); > + amdgpu_bo_unref(&queue->wptr_obj.obj); > amdgpu_userqueue_destroy_object(uq_mgr, &queue->fw_obj); > kfree(queue->userq_prop); > amdgpu_userqueue_destroy_object(uq_mgr, &queue->mqd); > diff --git a/drivers/gpu/drm/amd/include/amdgpu_userqueue.h b/drivers/gpu/drm/amd/include/amdgpu_userqueue.h > index 643f31474bd8..ffe8a3d73756 100644 > --- a/drivers/gpu/drm/amd/include/amdgpu_userqueue.h > +++ b/drivers/gpu/drm/amd/include/amdgpu_userqueue.h > @@ -45,6 +45,7 @@ struct amdgpu_usermode_queue { > struct amdgpu_vm *vm; > struct amdgpu_userq_obj mqd; > struct amdgpu_userq_obj fw_obj; > + struct amdgpu_userq_obj wptr_obj; > }; > > struct amdgpu_userq_funcs {