From: Luben Tuikov <luben.tuikov@amd.com>
To: "Russell, Kent" <Kent.Russell@amd.com>,
"amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>
Cc: "Deucher, Alexander" <Alexander.Deucher@amd.com>
Subject: Re: [PATCH 1/5] drm/amd/pm: Slight function rename
Date: Wed, 13 Oct 2021 10:53:12 -0400 [thread overview]
Message-ID: <9d1f5166-e72b-2f24-7194-131af3ae851c@amd.com> (raw)
In-Reply-To: <DM6PR12MB3324B58464F55888B4D1FF5285B79@DM6PR12MB3324.namprd12.prod.outlook.com>
On 2021-10-13 10:50, Russell, Kent wrote:
> [AMD Official Use Only]
>
> Pedantic tiny thing:
>
>> -----Original Message-----
>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Luben Tuikov
>> Sent: Tuesday, October 12, 2021 11:11 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Tuikov, Luben
>> <Luben.Tuikov@amd.com>
>> Subject: [PATCH 1/5] drm/amd/pm: Slight function rename
>>
>> Rename
>> sienna_cichlid_is_support_fine_grained_dpm() to
>> sienna_cichlid_support_fine_grained_dpm().
> ^You would want cichlid_supports_fine_grained_dpm . The function is correct below, but anyone grepping git logs would miss it.
Ah, yes, thank you Kent--I'll fix the description to add the missing 's'.
Regards,
Luben
>
> Kent
>
>> Rename
>> navi10_is_support_fine_grained_dpm() to
>> navi10_supports_fine_grained_dpm().
>>
>> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com>
>> ---
>> drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 7 ++++---
>> drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 7 ++++---
>> 2 files changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> index 71161f6b78fea9..0fe9790f67f5af 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
>> @@ -1231,7 +1231,8 @@ static int navi10_get_current_clk_freq_by_table(struct
>> smu_context *smu,
>> value);
>> }
>>
>> -static bool navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum
>> smu_clk_type clk_type)
>> +static bool navi10_supports_fine_grained_dpm(struct smu_context *smu,
>> + enum smu_clk_type clk_type)
>> {
>> PPTable_t *pptable = smu->smu_table.driver_pptable;
>> DpmDescriptor_t *dpm_desc = NULL;
>> @@ -1299,7 +1300,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,
>> if (ret)
>> return size;
>>
>> - if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) {
>> + if (!navi10_supports_fine_grained_dpm(smu, clk_type)) {
>> for (i = 0; i < count; i++) {
>> ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i,
>> &value);
>> if (ret)
>> @@ -1465,7 +1466,7 @@ static int navi10_force_clk_levels(struct smu_context *smu,
>> case SMU_UCLK:
>> case SMU_FCLK:
>> /* There is only 2 levels for fine grained DPM */
>> - if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
>> + if (navi10_supports_fine_grained_dpm(smu, clk_type)) {
>> soft_max_level = (soft_max_level >= 1 ? 1 : 0);
>> soft_min_level = (soft_min_level >= 1 ? 1 : 0);
>> }
>> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
>> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
>> index 15e66e1912de33..3f5721baa5ff50 100644
>> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
>> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
>> @@ -1006,7 +1006,8 @@ static int sienna_cichlid_get_current_clk_freq_by_table(struct
>> smu_context *smu,
>>
>> }
>>
>> -static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum
>> smu_clk_type clk_type)
>> +static bool sienna_cichlid_supports_fine_grained_dpm(struct smu_context *smu,
>> + enum smu_clk_type clk_type)
>> {
>> DpmDescriptor_t *dpm_desc = NULL;
>> DpmDescriptor_t *table_member;
>> @@ -1084,7 +1085,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context
>> *smu,
>> if (ret)
>> goto print_clk_out;
>>
>> - if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
>> + if (!sienna_cichlid_supports_fine_grained_dpm(smu, clk_type)) {
>> for (i = 0; i < count; i++) {
>> ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i,
>> &value);
>> if (ret)
>> @@ -1235,7 +1236,7 @@ static int sienna_cichlid_force_clk_levels(struct smu_context
>> *smu,
>> case SMU_UCLK:
>> case SMU_FCLK:
>> /* There is only 2 levels for fine grained DPM */
>> - if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
>> + if (sienna_cichlid_supports_fine_grained_dpm(smu, clk_type)) {
>> soft_max_level = (soft_max_level >= 1 ? 1 : 0);
>> soft_min_level = (soft_min_level >= 1 ? 1 : 0);
>> }
>> --
>> 2.33.1.558.g2bd2f258f4
next prev parent reply other threads:[~2021-10-13 14:53 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-13 3:10 [PATCH 0/5] 0 MHz is not a valid current frequency Luben Tuikov
2021-10-13 3:10 ` [PATCH 1/5] drm/amd/pm: Slight function rename Luben Tuikov
2021-10-13 14:50 ` Russell, Kent
2021-10-13 14:53 ` Luben Tuikov [this message]
2021-10-18 22:52 ` Paul Menzel
2021-10-18 23:02 ` Luben Tuikov
2021-10-13 3:10 ` [PATCH 2/5] drm/amd/pm: Rename cur_value to curr_value Luben Tuikov
2021-10-13 3:10 ` [PATCH 3/5] drm/amd/pm: Rename freq_values --> freq_value Luben Tuikov
2021-10-13 3:10 ` [PATCH 4/5] dpm/amd/pm: Sienna: 0 MHz is not a current clock frequency Luben Tuikov
2021-10-13 3:10 ` [PATCH 5/5] dpm/amd/pm: Navi10: " Luben Tuikov
2021-10-13 4:14 ` [PATCH 0/5] 0 MHz is not a valid current frequency Lazar, Lijo
2021-10-13 7:06 ` Quan, Evan
2021-10-13 13:58 ` Alex Deucher
2021-10-13 14:17 ` Lazar, Lijo
2021-10-13 16:22 ` Luben Tuikov
2021-10-13 17:06 ` Lazar, Lijo
2021-10-13 17:19 ` Alex Deucher
2021-10-15 2:25 ` Quan, Evan
2021-10-18 20:19 ` Deucher, Alexander
2021-10-18 20:29 ` Luben Tuikov
2021-10-19 1:04 ` Russell, Kent
2021-10-19 1:06 ` Russell, Kent
2021-10-19 4:27 ` Luben Tuikov
2021-10-19 13:25 ` Russell, Kent
2021-10-19 13:54 ` Luben Tuikov
2021-10-26 21:26 ` Alex Deucher
2021-10-26 22:00 ` Luben Tuikov
2021-10-27 5:20 ` Lazar, Lijo
2021-10-27 15:12 ` Alex Deucher
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