amd-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: Alex Deucher <alexdeucher@gmail.com>
To: "Timur Kristóf" <timur.kristof@gmail.com>
Cc: "Christian König" <christian.koenig@amd.com>,
	amd-gfx@lists.freedesktop.org,
	"Alex Deucher" <alexander.deucher@amd.com>,
	"Alexandre Demers" <alexandre.f.demers@gmail.com>,
	"Rodrigo Siqueira" <siqueira@igalia.com>,
	"Leo Liu" <Leo.Liu@amd.com>
Subject: Re: [PATCH 09/16] drm/amdgpu/si, cik, vi: Verify IP block when querying video codecs (v2)
Date: Tue, 4 Nov 2025 10:27:57 -0500	[thread overview]
Message-ID: <CADnq5_ONzWm3uNNo2gdScuDRMjqtoJ5RfTOqna7aTSok_vEwuQ@mail.gmail.com> (raw)
In-Reply-To: <01cfdc57f76218039efb67226b9c08189f8a1b1e.camel@gmail.com>

On Tue, Nov 4, 2025 at 10:16 AM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On Tue, 2025-11-04 at 14:44 +0100, Christian König wrote:
> > On 11/3/25 23:23, Timur Kristóf wrote:
> > > Some harvested chips may not have any IP blocks,
> > > or we may not have the firmware for the IP blocks.
> > > In these cases, the query should return that no video
> > > codec is supported.
> > >
> > > v2:
> > > - When codecs is NULL, treat that as empty codec list.
> >
> > I'm still not sure if returning an error instead wouldn't be better.
> >
> > @Alex and Leo what do you guys think?
> >
> > Regards,
> > Christian.
>
> Returning an error from this function would indicate to userspace that
> there was an error with querying the list of codecs.
>
> That is not what we want. We simply want to tell userspace that no
> codecs are supported.

If the IP is harvested or if it's been disabled, we wouldn't be
exposing any rings via drm_amdgpu_info_hw_ip so I don't think we need
this.

Alex

>
> Thanks & best regards,
> Timur
>
>
> >
> > >
> > > Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 7 +++++--
> > >  drivers/gpu/drm/amd/amdgpu/cik.c        | 6 ++++++
> > >  drivers/gpu/drm/amd/amdgpu/si.c         | 6 ++++++
> > >  drivers/gpu/drm/amd/amdgpu/vi.c         | 6 ++++++
> > >  4 files changed, 23 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > index b3e6b3fcdf2c..71eceac58fb6 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> > > @@ -1263,8 +1263,9 @@ int amdgpu_info_ioctl(struct drm_device *dev,
> > > void *data, struct drm_file *filp)
> > >                     -EFAULT : 0;
> > >     }
> > >     case AMDGPU_INFO_VIDEO_CAPS: {
> > > -           const struct amdgpu_video_codecs *codecs;
> > > +           const struct amdgpu_video_codecs *codecs = NULL;
> > >             struct drm_amdgpu_info_video_caps *caps;
> > > +           u32 codec_count;
> > >             int r;
> > >
> > >             if (!adev->asic_funcs->query_video_codecs)
> > > @@ -1291,7 +1292,9 @@ int amdgpu_info_ioctl(struct drm_device *dev,
> > > void *data, struct drm_file *filp)
> > >             if (!caps)
> > >                     return -ENOMEM;
> > >
> > > -           for (i = 0; i < codecs->codec_count; i++) {
> > > +           codec_count = codecs ? codecs->codec_count : 0;
> > > +
> > > +           for (i = 0; i < codec_count; i++) {
> > >                     int idx = codecs-
> > > >codec_array[i].codec_type;
> > >
> > >                     switch (idx) {
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
> > > b/drivers/gpu/drm/amd/amdgpu/cik.c
> > > index 9cd63b4177bf..b755238c2c3d 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> > > @@ -130,6 +130,12 @@ static const struct amdgpu_video_codecs
> > > cik_video_codecs_decode =
> > >  static int cik_query_video_codecs(struct amdgpu_device *adev, bool
> > > encode,
> > >                               const struct amdgpu_video_codecs
> > > **codecs)
> > >  {
> > > +   const enum amd_ip_block_type ip =
> > > +           encode ? AMD_IP_BLOCK_TYPE_VCE :
> > > AMD_IP_BLOCK_TYPE_UVD;
> > > +
> > > +   if (!amdgpu_device_ip_is_valid(adev, ip))
> > > +           return 0;
> > > +
> > >     switch (adev->asic_type) {
> > >     case CHIP_BONAIRE:
> > >     case CHIP_HAWAII:
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/si.c
> > > b/drivers/gpu/drm/amd/amdgpu/si.c
> > > index e0f139de7991..9468c03bdb1b 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/si.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> > > @@ -1003,6 +1003,12 @@ static const struct amdgpu_video_codecs
> > > hainan_video_codecs_decode =
> > >  static int si_query_video_codecs(struct amdgpu_device *adev, bool
> > > encode,
> > >                              const struct amdgpu_video_codecs
> > > **codecs)
> > >  {
> > > +   const enum amd_ip_block_type ip =
> > > +           encode ? AMD_IP_BLOCK_TYPE_VCE :
> > > AMD_IP_BLOCK_TYPE_UVD;
> > > +
> > > +   if (!amdgpu_device_ip_is_valid(adev, ip))
> > > +           return 0;
> > > +
> > >     switch (adev->asic_type) {
> > >     case CHIP_VERDE:
> > >     case CHIP_TAHITI:
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c
> > > b/drivers/gpu/drm/amd/amdgpu/vi.c
> > > index a611a7345125..f0e4193cf722 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/vi.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/vi.c
> > > @@ -256,6 +256,12 @@ static const struct amdgpu_video_codecs
> > > cz_video_codecs_decode =
> > >  static int vi_query_video_codecs(struct amdgpu_device *adev, bool
> > > encode,
> > >                              const struct amdgpu_video_codecs
> > > **codecs)
> > >  {
> > > +   const enum amd_ip_block_type ip =
> > > +           encode ? AMD_IP_BLOCK_TYPE_VCE :
> > > AMD_IP_BLOCK_TYPE_UVD;
> > > +
> > > +   if (!amdgpu_device_ip_is_valid(adev, ip))
> > > +           return 0;
> > > +
> > >     switch (adev->asic_type) {
> > >     case CHIP_TOPAZ:
> > >             if (encode)

  reply	other threads:[~2025-11-04 15:28 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03 22:23 [PATCH 00/16] drm/amdgpu: Support VCE1 IP block (v2) Timur Kristóf
2025-11-03 22:23 ` [PATCH 01/16] drm/amdgpu/gmc: Don't hardcode GART page count before GTT Timur Kristóf
2025-11-04 13:23   ` Christian König
2025-11-04 15:08     ` Pierre-Eric Pelloux-Prayer
2025-11-04 15:24       ` Christian König
2025-11-04 15:37         ` Pierre-Eric Pelloux-Prayer
2025-11-04 15:26       ` Timur Kristóf
2025-11-04 17:10         ` Timur Kristóf
2025-11-03 22:23 ` [PATCH 02/16] drm/amdgpu/gmc6: Place gart at low address range Timur Kristóf
2025-11-03 22:23 ` [PATCH 03/16] drm/amdgpu/gmc6: Add GART space for VCPU BO (v2) Timur Kristóf
2025-11-03 22:23 ` [PATCH 04/16] drm/amdgpu/gart: Add helper to bind VRAM pages (v2) Timur Kristóf
2025-11-04 13:32   ` Christian König
2025-11-03 22:23 ` [PATCH 05/16] drm/amdgpu/ttm: Use GART helper to map " Timur Kristóf
2025-11-04 13:33   ` Christian König
2025-11-04 15:11     ` Timur Kristóf
2025-11-03 22:23 ` [PATCH 06/16] drm/amdgpu/vce: Clear VCPU BO before copying firmware to it (v2) Timur Kristóf
2025-11-03 22:23 ` [PATCH 07/16] drm/amdgpu/vce: Move firmware load to amdgpu_vce_early_init Timur Kristóf
2025-11-03 22:23 ` [PATCH 08/16] drm/amdgpu/vce: Save/restore and pin VCPU BO for all VCE (v2) Timur Kristóf
2025-11-03 22:23 ` [PATCH 09/16] drm/amdgpu/si, cik, vi: Verify IP block when querying video codecs (v2) Timur Kristóf
2025-11-04 13:44   ` Christian König
2025-11-04 15:16     ` [PATCH 09/16] drm/amdgpu/si,cik,vi: " Timur Kristóf
2025-11-04 15:27       ` Alex Deucher [this message]
2025-11-04 15:29         ` [PATCH 09/16] drm/amdgpu/si, cik, vi: " Christian König
2025-11-04 15:33           ` Alex Deucher
2025-11-03 22:23 ` [PATCH 10/16] drm/amdgpu/vce1: Clean up register definitions Timur Kristóf
2025-11-03 22:23 ` [PATCH 11/16] drm/amdgpu/vce1: Load VCE1 firmware Timur Kristóf
2025-11-03 22:23 ` [PATCH 12/16] drm/amdgpu/vce1: Implement VCE1 IP block (v2) Timur Kristóf
2025-11-04 13:51   ` Christian König
2025-11-03 22:23 ` [PATCH 13/16] drm/amdgpu/vce1: Ensure VCPU BO is in lower 32-bit address space (v2) Timur Kristóf
2025-11-03 22:23 ` [PATCH 14/16] drm/amd/pm/si: Hook up VCE1 to SI DPM Timur Kristóf
2025-11-03 22:23 ` [PATCH 15/16] drm/amdgpu/vce1: Enable VCE1 on Tahiti, Pitcairn, Cape Verde GPUs Timur Kristóf
2025-11-03 22:23 ` [PATCH 16/16] drm/amdgpu/vce1: Workaround PLL timeout on FirePro W9000 Timur Kristóf

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CADnq5_ONzWm3uNNo2gdScuDRMjqtoJ5RfTOqna7aTSok_vEwuQ@mail.gmail.com \
    --to=alexdeucher@gmail.com \
    --cc=Leo.Liu@amd.com \
    --cc=alexander.deucher@amd.com \
    --cc=alexandre.f.demers@gmail.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=christian.koenig@amd.com \
    --cc=siqueira@igalia.com \
    --cc=timur.kristof@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).