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To: =?UTF-8?Q?Timur_Krist=C3=B3f?= , "Wentland, Harry" , "Leo (Sunpeng) Li" Cc: amd-gfx@lists.freedesktop.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Sat, Aug 2, 2025 at 11:58=E2=80=AFAM Timur Krist=C3=B3f wrote: > > On DCE 6, DP audio was not working. However, it worked when an > HDMI monitor was also plugged in. > > Looking at dce_aud_wall_dto_setup it seems that the main > difference is that we use DTO1 when only DP is plugged in. > > When programming DTO1, it uses audio_dto_source_clock_in_khz > which is set from get_dp_ref_freq_khz > > The dce60_get_dp_ref_freq_khz implementation looks incorrect, > because DENTIST_DISPCLK_CNTL seems to be always zero on DCE 6, > so it isn't usable. > I compared dce60_get_dp_ref_freq_khz to the legacy display code, > specifically dce_v6_0_audio_set_dto, and it turns out that in > case of DCE 6, it needs to use the display clock. With that, > DP audio started working on Pitcairn, Oland and Cape Verde. > > However, it still didn't work on Tahiti. Despite having the > same DCE version, Tahiti seems to have a different audio device. > After some trial and error I realized that it works with the > default display clock as reported by the VBIOS, not the current > display clock. > This looks good to me, but it would be good to get an ack from Harry or Leo= . Acked-by: Alex Deucher > The patch was tested on all four SI GPUs: > > * Pitcairn (DCE 6.0) > * Oland (DCE 6.4) > * Cape Verde (DCE 6.0) > * Tahiti (DCE 6.0 but different) > > The testing was done on Samsung Odyssey G7 LS28BG700EPXEN on > each of the above GPUs, at the following settings: > > * 4K 60 Hz > * 1080p 60 Hz > * 1080p 144 Hz > > Signed-off-by: Timur Krist=C3=B3f > --- > .../display/dc/clk_mgr/dce60/dce60_clk_mgr.c | 21 ++++++------------- > 1 file changed, 6 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c= b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c > index 0267644717b2..883591706db9 100644 > --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c > +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c > @@ -83,22 +83,13 @@ static const struct state_dependent_clocks dce60_max_= clks_by_state[] =3D { > static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) > { > struct clk_mgr_internal *clk_mgr =3D TO_CLK_MGR_INTERNAL(clk_mgr_= base); > - int dprefclk_wdivider; > - int dp_ref_clk_khz; > - int target_div; > + struct dc_context *ctx =3D clk_mgr_base->ctx; > + int dp_ref_clk_khz =3D 0; > > - /* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */ > - > - /* Read the mmDENTIST_DISPCLK_CNTL to get the currently > - * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ > - REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefcl= k_wdivider); > - > - /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ > - target_div =3D dentist_get_divider_from_did(dprefclk_wdivider); > - > - /* Calculate the current DFS clock, in kHz.*/ > - dp_ref_clk_khz =3D (DENTIST_DIVIDER_RANGE_SCALE_FACTOR > - * clk_mgr->base.dentist_vco_freq_khz) / target_div; > + if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev)) > + dp_ref_clk_khz =3D ctx->dc_bios->fw_info.default_display_= engine_pll_frequency; > + else > + dp_ref_clk_khz =3D clk_mgr_base->clks.dispclk_khz; > > return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz); > } > -- > 2.50.1 >