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Tue, 22 Apr 2025 08:59:05 -0700 (PDT) Received: from localhost ([2a00:2381:fd67:101:6c39:59e6:b76d:825]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4406d5d74a1sm176570345e9.37.2025.04.22.08.59.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Apr 2025 08:59:05 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 22 Apr 2025 16:59:04 +0100 Message-Id: Cc: "Fugang Duan" , "alexander.deucher@amd.com" , "frank.min@amd.com" , "amd-gfx@lists.freedesktop.org" , "stable@vger.kernel.org" , "david.belanger@amd.com" , "christian.koenig@amd.com" , "Peter Chen" , "cix-kernel-upstream" , "linux-arm-kernel@lists.infradead.org" Subject: =?utf-8?q?Re:_=E5=9B=9E=E5=A4=8D:_[REGRESSION]_amdgpu:_async_system_error?= =?utf-8?q?_exception_from_hdp=5Fv5=5F0=5Fflush=5Fhdp()?= From: "Alexey Klimov" To: "Alex Deucher" X-Mailer: aerc 0.20.0 References: In-Reply-To: X-Mailman-Approved-At: Wed, 23 Apr 2025 07:38:20 +0000 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Tue Apr 22, 2025 at 2:00 PM BST, Alex Deucher wrote: > On Mon, Apr 21, 2025 at 10:21=E2=80=AFPM Alexey Klimov wrote: >> >> On Thu Apr 17, 2025 at 2:08 PM BST, Alex Deucher wrote: >> > On Wed, Apr 16, 2025 at 8:43=E2=80=AFPM Fugang Duan wrote: >> >> >> >> =E5=8F=91=E4=BB=B6=E4=BA=BA: Alex Deucher =E5= =8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2025=E5=B9=B44=E6=9C=8816=E6=97=A5 22:49 >> >> >=E6=94=B6=E4=BB=B6=E4=BA=BA: Alexey Klimov >> >> >On Wed, Apr 16, 2025 at 9:48=E2=80=AFAM Alexey Klimov wrote: >> >> >> >> >> >> On Wed Apr 16, 2025 at 4:12 AM BST, Fugang Duan wrote: >> >> >> > =E5=8F=91=E4=BB=B6=E4=BA=BA: Alexey Klimov =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2025=E5=B9=B44=E6=9C=8816 >> >> >=E6=97=A5 2:28 >> >> >> >>#regzbot introduced: v6.12..v6.13 >> >> >> >>The only change related to hdp_v5_0_flush_hdp() was >> >> >> >>cf424020e040 drm/amdgpu/hdp5.0: do a posting read when flushing = HDP >> >> >> >> >> >> >> >>Reverting that commit ^^ did help and resolved that problem. Bef= ore [..] >> > OK. that patch won't change anything then. Can you try this patch in= stead? >> >> Config I am using is basically defconfig wrt memory parameters, yeah, i = use 4k. >> >> So I tested that patch, thank you, and some other different configuratio= ns -- >> nothing helped. Exactly the same behaviour with the same backtrace. > > Did you test the first (4k check) or the second (don't remap on ARM) patc= h? The second one. I think you mentioned that first one won't help for 4k page= s. >> So it seems that it is firmware problem after all? > > There is no GPU firmware involved in this operation. It's just a > posted write. E.g., we write to a register to flush the HDP write > queue and then read the register back to make sure the write posted. > If the second patch didn't help, then perhaps there is some issue with > MMIO access on your platform? I didn't mean GPU firmware at all. I only had uefi/EL3 firmwares in mind. Completely out of the blue, based on nothing, do you think that adding delay/some mem barrier between write and read might help? I wonder if host data path code should be executed during common desktop usage as a common user then why it doesn't break later. But yeah, I also think this is this motherboard problem. Thank you. Thanks, Alexey