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[142.127.77.63]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-988b86d6058sm952145241.0.2026.09.28.12.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 12:08:40 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: natalie.vock@gmx.de, honghuan@amd.com, Alexander.Deucher@amd.com, Felix.Kuehling@amd.com, Philip.Yang@amd.com, cascardo@igalia.com, tvrtko.ursulin@igalia.com, christian.koenig@amd.com Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 2/9] drm/amdgpu: fix cleared PDE/PTE flag generation Date: Mon, 28 Sep 2026 15:08:39 -0400 Message-ID: In-Reply-To: <20260928151041.1857-2-christian.koenig@amd.com> References: <20260928151041.1857-1-christian.koenig@amd.com> <20260928151041.1857-2-christian.koenig@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. szeptember 28., h=C3=A9tf=C5=91 11:10:34 keleti =C3=A1llamokbeli n= y=C3=A1ri id=C5=91 Christian=20 K=C3=B6nig wrote: > That was broken since adding the NPA support. >=20 > Signed-off-by: Christian K=C3=B6nig Reviewed-by: Timur Krist=C3=B3f > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 64 ++++++++++++----------- > 1 file changed, 33 insertions(+), 31 deletions(-) >=20 > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index > c03327f1242d3..e8f441e018839 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c > @@ -346,6 +346,33 @@ static void amdgpu_vm_pt_next_dfs(struct amdgpu_devi= ce > *adev, amdgpu_vm_pt_continue_dfs((start), (entry)); =09 \ > (entry) =3D (cursor).entry, amdgpu_vm_pt_next_dfs((adev),=20 &(cursor))) >=20 > +/* Return the flags used for cleared PDEs/PTES */ > +static uint64_t amdgpu_vm_pt_clear_flags(struct amdgpu_device *adev, > + struct amdgpu_vm *vm, > + unsigned int level) > +{ > + uint64_t flags; > + > + if (adev->asic_type < CHIP_VEGA10) > + return 0; > + > + if (level !=3D AMDGPU_VM_PTB) { > + uint64_t value =3D 0; > + > + flags =3D AMDGPU_PDE_PTE_FLAG(adev); > + if (vm->is_npa) > + flags |=3D adev->gmc.noretry_flags; > + amdgpu_gmc_get_vm_pde(adev, level, &value, &flags); > + } else if (vm->is_npa) { > + flags =3D adev->gmc.noretry_flags; > + } else { > + /* Workaround for fault priority problem on GMC9 */ > + flags =3D AMDGPU_PTE_EXECUTABLE | adev->gmc.init_pte_flags; > + } > + > + return flags; > +} > + > /** > * amdgpu_vm_pt_clear - initially clear the PDs/PTs > * > @@ -366,10 +393,9 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, > struct amdgpu_vm *vm, struct ttm_operation_ctx ctx =3D { true, false }; > struct amdgpu_vm_update_params params; > struct amdgpu_bo *ancestor =3D &vmbo->bo; > - unsigned int entries; > struct amdgpu_bo *bo =3D &vmbo->bo; > - uint64_t value =3D 0, flags =3D 0; > - uint64_t addr; > + unsigned int entries; > + uint64_t flags; > int r, idx; >=20 > /* Figure out our place in the hierarchy */ > @@ -404,26 +430,8 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, > struct amdgpu_vm *vm, if (r) > goto exit; >=20 > - addr =3D 0; > - > - if (adev->asic_type >=3D CHIP_VEGA10) { > - if (level !=3D AMDGPU_VM_PTB) { > - if (vm->is_npa) > - flags =3D adev->gmc.noretry_flags; > - /* Handle leaf PDEs as PTEs */ > - flags |=3D AMDGPU_PDE_PTE_FLAG(adev); > - amdgpu_gmc_get_vm_pde(adev, level, > - &value, &flags); > - } else if (vm->is_npa) { > - flags =3D adev->gmc.noretry_flags; > - } else { > - /* Workaround for fault priority problem on=20 GMC9 */ > - flags =3D AMDGPU_PTE_EXECUTABLE | adev- >gmc.init_pte_flags; > - } > - } > - > - r =3D vm->update_funcs->update(¶ms, vmbo, addr, 0, entries, > - value, flags); > + flags =3D amdgpu_vm_pt_clear_flags(adev, vm, level); > + r =3D vm->update_funcs->update(¶ms, vmbo, 0, 0, entries, 0,=20 flags); > if (r) > goto exit; >=20 > @@ -712,15 +720,9 @@ static void amdgpu_vm_pte_update_flags(struct > amdgpu_vm_update_params *params, flags |=3D > AMDGPU_PDE_PTE_FLAG(params->adev); > amdgpu_gmc_get_vm_pde(adev, level, &addr, &flags); >=20 > - } else if (adev->asic_type >=3D CHIP_VEGA10 && > - !(flags & AMDGPU_PTE_VALID) && > + } else if (!(flags & AMDGPU_PTE_VALID) && > !(flags & AMDGPU_PTE_PRT_FLAG(params->adev))) { > - > - /* Workaround for fault priority problem on GMC9 and=20 GFX12, > - * EXECUTABLE for GMC9 fault priority and init_pte_flags > - * (e.g. AMDGPU_PTE_IS_PTE on GFX12) > - */ > - flags |=3D AMDGPU_PTE_EXECUTABLE | adev- >gmc.init_pte_flags; > + flags |=3D amdgpu_vm_pt_clear_flags(adev, params->vm,=20 level); > } >=20 > /*