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[79.129.254.8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49d03543064sm238956215e9.13.2026.09.07.11.31.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Sep 2026 11:31:57 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alexander.Deucher@amd.com, Christian =?UTF-8?B?S8O2bmln?= , Natalie Vock , Tvrtko Ursulin , Felix Kuehling , "Lazar, Lijo" Subject: Re: [PATCH 5/8] drm/amdgpu/sdma: Clear SDMA rings after reset before starting them Date: Mon, 07 Sep 2026 20:31:55 +0200 Message-ID: In-Reply-To: References: <20260904072850.321759-1-timur.kristof@gmail.com> <20260904072850.321759-6-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. szeptember 7., h=C3=A9tf=C5=91 9:04:55 k=C3=B6z=C3=A9p-eur=C3=B3pa= i ny=C3=A1ri id=C5=91 Lazar, Lijo=20 wrote: > On 04-Sep-26 12:58 PM, Timur Krist=C3=B3f wrote: > > The ring contains commands that were emitted before the reset. > > These need to be cleared to make sure the HW doesn't execute > > them, because they are garbage at this point. > >=20 > > Note that the ring reset helpers will re-emit the commands > > that are necessary after the reset. > >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c index > > fbac732f3e01..66f278f77f71 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c > > @@ -593,6 +593,18 @@ int amdgpu_sdma_reset_engine(struct amdgpu_device > > *adev, uint32_t instance_id,>=20 > > goto exit; > > =09 > > } > >=20 > > + amdgpu_ring_clear_ring(gfx_ring); > > + gfx_ring->wptr =3D 0; > > + atomic64_set((atomic64_t *)gfx_ring->wptr_cpu_addr, 0); > > + atomic64_set((atomic64_t *)gfx_ring->rptr_cpu_addr, 0); > > + > > + if (adev->sdma.has_page_queue) { > > + amdgpu_ring_clear_ring(page_ring); > > + page_ring->wptr =3D 0; > > + atomic64_set((atomic64_t *)page_ring->wptr_cpu_addr,=20 0); > > + atomic64_set((atomic64_t *)page_ring->rptr_cpu_addr,=20 0); > > + } >=20 > This could be made as a small inline function like > amdgpu_ring_reset_ptr(ring); >=20 > Thanks, > Lijo Thank you for the suggestion, I'll add that to the next version of the seri= es. >=20 > > + > >=20 > > if (sdma_instance->funcs->start_kernel_queue) { > > =09 > > sdma_instance->funcs->start_kernel_queue(gfx_ring); > > if (adev->sdma.has_page_queue)