Re: [PATCH 4/4] drm/amdgpu/vcn3.0: remove intermediate variable

[Leo Liu <leo.liu@amd.com>]

The series are:

Reviewed-by: Leo Liu <leo.liu@amd.com>

On 2021-10-19 4:10 p.m., Alex Deucher wrote:
> No need to use the id variable, just use the constant
> plus instance offset directly.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 11 ++---------
>   1 file changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index 57b62fb04750..da11ceba0698 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -60,11 +60,6 @@ static int amdgpu_ih_clientid_vcns[] = {
>   	SOC15_IH_CLIENTID_VCN1
>   };
>   
> -static int amdgpu_ucode_id_vcns[] = {
> -	AMDGPU_UCODE_ID_VCN,
> -	AMDGPU_UCODE_ID_VCN1
> -};
> -
>   static int vcn_v3_0_start_sriov(struct amdgpu_device *adev);
>   static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>   static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev);
> @@ -1278,7 +1273,6 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
>   	uint32_t param, resp, expected;
>   	uint32_t offset, cache_size;
>   	uint32_t tmp, timeout;
> -	uint32_t id;
>   
>   	struct amdgpu_mm_table *table = &adev->virt.mm_table;
>   	uint32_t *table_loc;
> @@ -1322,13 +1316,12 @@ static int vcn_v3_0_start_sriov(struct amdgpu_device *adev)
>   		cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
>   
>   		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> -			id = amdgpu_ucode_id_vcns[i];
>   			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
>   				mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> -				adev->firmware.ucode[id].tmr_mc_addr_lo);
> +				adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo);
>   			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
>   				mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> -				adev->firmware.ucode[id].tmr_mc_addr_hi);
> +				adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi);
>   			offset = 0;
>   			MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,
>   				mmUVD_VCPU_CACHE_OFFSET0),