From: "Christian König" <christian.koenig@amd.com>
To: "Timur Kristóf" <timur.kristof@gmail.com>,
amd-gfx@lists.freedesktop.org, alexander.deucher@amd.com,
"John Olender" <john.olender@gmail.com>
Subject: Re: [PATCH 01/11] drm/amdgpu: Align amdgpu_gtt_mgr entries to TLB size on Tahiti
Date: Thu, 23 Apr 2026 13:04:53 +0200 [thread overview]
Message-ID: <a3dc4b02-505a-4547-885a-ab585310e652@amd.com> (raw)
In-Reply-To: <20260423011614.309180-2-timur.kristof@gmail.com>
On 4/23/26 03:16, Timur Kristóf wrote:
> The TLB is organized in groups of 8 entries, each one is 4K.
> On Tahiti, the HW requires these GART entries to be 32K-aligned.
>
> This fixes a VCE 1 firmware validation failure that can happen
> after suspend/resume since we use amdgpu_gtt_mgr for VCE 1.
>
> Fixes: 698fa62f56aa ("drm/amdgpu: Add helper to alloc GART entries")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index 9b0bcf6aca445..673e9e08c66a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -198,12 +198,19 @@ int amdgpu_gtt_mgr_alloc_entries(struct amdgpu_gtt_mgr *mgr,
> u64 num_pages,
> enum drm_mm_insert_mode mode)
> {
> + u32 alignment = 0;
> struct amdgpu_device *adev = container_of(mgr, typeof(*adev), mman.gtt_mgr);
> int r;
Only a nit, but reverse xmas tree order please for variable declarations.
>
> + /* Align to TLB size on Tahiti */
Oh that needs improvement.
Maybe something like /* Align to TLB L2 cache entry size to work around V bit HW bug */
Mostly nobody will know what that "V bit HW bug" is, but at least AMD people can search for that in the HW docs.
With that fixed Reviewed-by: Christian König <christian.koenig@amd.com>.
Thanks,
Christian.
> + if (adev->asic_type == CHIP_TAHITI) {
> + alignment = 32 * 1024 / AMDGPU_GPU_PAGE_SIZE;
> + num_pages = ALIGN(num_pages, alignment);
> + }
> +
> spin_lock(&mgr->lock);
> r = drm_mm_insert_node_in_range(&mgr->mm, mm_node, num_pages,
> - 0, GART_ENTRY_WITHOUT_BO_COLOR, 0,
> + alignment, GART_ENTRY_WITHOUT_BO_COLOR, 0,
> adev->gmc.gart_size >> PAGE_SHIFT,
> mode);
> spin_unlock(&mgr->lock);
next prev parent reply other threads:[~2026-04-23 11:05 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-23 1:16 [PATCH 00/11] VCE1 fixes (v2) Timur Kristóf
2026-04-23 1:16 ` [PATCH 01/11] drm/amdgpu: Align amdgpu_gtt_mgr entries to TLB size on Tahiti Timur Kristóf
2026-04-23 11:04 ` Christian König [this message]
2026-04-23 12:18 ` Timur Kristóf
2026-04-23 13:32 ` Christian König
2026-04-23 1:16 ` [PATCH 02/11] drm/amdgpu/vce1: Check that the GPU address is < 128 MiB Timur Kristóf
2026-04-23 11:06 ` Christian König
2026-04-23 1:16 ` [PATCH 03/11] drm/amdgpu/vce1: Remove superfluous address check Timur Kristóf
2026-04-23 1:16 ` [PATCH 04/11] drm/amdgpu/vce1: Check if VRAM address is lower than GART Timur Kristóf
2026-04-23 1:16 ` [PATCH 05/11] drm/amdgpu/vce1: Don't repeat GTT MGR node allocation Timur Kristóf
2026-04-23 1:16 ` [PATCH 06/11] drm/amdgpu/vce1: Fix VCE 1 firmware size and offsets Timur Kristóf
2026-04-23 11:12 ` Christian König
2026-04-23 1:16 ` [PATCH 07/11] drm/amdgpu/vce1: Stop using amdgpu_vce_resume Timur Kristóf
2026-04-23 11:13 ` Christian König
2026-04-23 1:16 ` [PATCH 08/11] drm/amdgpu/vce: Check maximum ucode size in amdgpu_vce_resume() Timur Kristóf
2026-04-23 1:16 ` [PATCH 09/11] drm/amdgpu/vce2: Fix VCE 2 firmware size and offsets Timur Kristóf
2026-04-23 11:28 ` Christian König
2026-04-23 18:10 ` John Olender
2026-04-23 1:16 ` [PATCH 10/11] drm/amdgpu/vce3: Fix VCE 3 " Timur Kristóf
2026-04-23 11:29 ` Christian König
2026-04-23 1:16 ` [PATCH 11/11] drm/amdgpu/vce4: Fix VCE 4 " Timur Kristóf
2026-04-23 11:31 ` Christian König
2026-04-23 11:50 ` Timur Kristóf
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