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([2a02:908:1252:fb60:8a1c:e700:29c4:44b6]) by smtp.gmail.com with ESMTPSA id s7sm1230483ejd.88.2021.06.24.06.01.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Jun 2021 06:01:36 -0700 (PDT) Subject: Re: [PATCH v2] drm/amdgpu: Restore msix after FLR To: Peng Ju Zhou , amd-gfx@lists.freedesktop.org References: <20210624053132.3458-1-PengJu.Zhou@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= Message-ID: Date: Thu, 24 Jun 2021 15:01:36 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210624053132.3458-1-PengJu.Zhou@amd.com> Content-Language: en-US X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Emily.Deng" Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 24.06.21 um 07:31 schrieb Peng Ju Zhou: > From: "Emily.Deng" > > After FLR, the msix will be cleared, so need to re-enable it. > > Signed-off-by: Emily.Deng > Signed-off-by: Peng Ju Zhou > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c > index 90f50561b43a..ba9edafd4fc6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c > @@ -277,6 +277,18 @@ static bool amdgpu_msi_ok(struct amdgpu_device *adev) > return true; > } > > +void amdgpu_restore_msix(struct amdgpu_device *adev) > +{ > +#ifdef PCI_IRQ_MSIX Please drop that ifdef, the macro is always defined upstream. Christian. > + u16 ctrl; > + > + pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); > + ctrl &= ~PCI_MSIX_FLAGS_ENABLE; > + pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); > + ctrl |= PCI_MSIX_FLAGS_ENABLE; > + pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl); > +#endif > +} > /** > * amdgpu_irq_init - initialize interrupt handling > * > @@ -558,6 +570,7 @@ void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev) > { > int i, j, k; > > + amdgpu_restore_msix(adev); > for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) { > if (!adev->irq.client[i].sources) > continue; _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx