From: Sultan Alsawaf <sultan@kerneltoast.com>
To: Mario Limonciello <mario.limonciello@amd.com>
Cc: amd-gfx@lists.freedesktop.org, Peyton.Lee@amd.com
Subject: Re: [PATCH v5] drm/amd: Check that VPE has reached DPM0 in idle handler
Date: Sun, 19 Oct 2025 15:25:57 -0700 [thread overview]
Message-ID: <aPVldXCcgipLn6Dg@sultan-box> (raw)
In-Reply-To: <20251016185527.1796606-1-mario.limonciello@amd.com>
On Thu, Oct 16, 2025 at 01:55:27PM -0500, Mario Limonciello wrote:
> [Why]
> Newer VPE microcode has functionality that will decrease DPM level
> only when a workload has run for 2 or more seconds. If VPE is turned
> off before this DPM decrease and the PMFW doesn't reset it when
> power gating VPE, the SOC can get stuck with a higher DPM level.
>
> This can happen from amdgpu's ring buffer test because it's a short
> quick workload for VPE and VPE is turned off after 1s.
>
> [How]
> In idle handler besides checking fences are drained check PMFW version
> to determine if it will reset DPM when power gating VPE. If PMFW will
> not do this, then check VPE DPM level. If it is not DPM0 reschedule
> delayed work again until it is.
>
> Cc: Peyton.Lee@amd.com
> Reported-by: Sultan Alsawaf <sultan@kerneltoast.com>
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4615
> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-and-tested-by: Sultan Alsawaf <sultan@kerneltoast.com>
Thanks again for fixing this.
Sultan
next prev parent reply other threads:[~2025-10-20 12:48 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 18:55 [PATCH v5] drm/amd: Check that VPE has reached DPM0 in idle handler Mario Limonciello
2025-10-17 4:08 ` Lazar, Lijo
2025-10-19 22:25 ` Sultan Alsawaf [this message]
2025-10-20 21:56 ` Sultan Alsawaf
2025-10-20 21:58 ` Mario Limonciello
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