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From: "Cui, Flora" <fcui-5C7GfCeVMHo@public.gmane.org>
To: "Huang, Ray" <Ray.Huang-5C7GfCeVMHo@public.gmane.org>,
	"Cui, Flora" <Flora.Cui-5C7GfCeVMHo@public.gmane.org>,
	"amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org"
	<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: "Zhu, Changfeng" <Changfeng.Zhu-5C7GfCeVMHo@public.gmane.org>
Subject: Re: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test
Date: Fri, 19 Jul 2019 09:55:27 +0000	[thread overview]
Message-ID: <aa64576a-4488-a116-a7d0-172ee8cdcf5b@amd.com> (raw)
In-Reply-To: <MN2PR12MB3309C72D7A8B590F848B19FBECCB0-rweVpJHSKTpWdvXm18W95QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>

I'm not sure. Could you have a try?

在 7/19/2019 3:48 PM, Huang, Ray 写道:
> Thanks Flora, can we have these tests, and try on our new APUs as well? 😊
>
> Thanks,
> Ray
>
>> -----Original Message-----
>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Cui,
>> Flora
>> Sent: Thursday, July 18, 2019 4:11 PM
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Cui, Flora <Flora.Cui@amd.com>
>> Subject: [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test
>>
>> 1. skip test if there's no desired ring
>> 2. clear shader buffer
>> 3. update command buffer for gfx9
>>
>> Change-Id: I5e4e92842c4fd1088c14dc048bedf4fe84892b36
>> Signed-off-by: Flora Cui <flora.cui@amd.com>
>> ---
>>   tests/amdgpu/basic_tests.c | 36 ++++++++++++++++++++++++++++--------
>>   1 file changed, 28 insertions(+), 8 deletions(-)
>>
>> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index
>> 2d47269..8fa7088 100644
>> --- a/tests/amdgpu/basic_tests.c
>> +++ b/tests/amdgpu/basic_tests.c
>> @@ -329,14 +329,15 @@ static const uint32_t preamblecache_gfx9[] = {
>>   	0xc0016900, 0x2d5, 0x10000, 0xc0016900,  0x2dc, 0x0,
>>   	0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5,
>> 0x0, 0x0,
>>   	0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000,
>> 0x3f800000,
>> -	0xc0026900, 0x311,  0x3, 0x0, 0xc0026900, 0x316, 0x1e, 0x20,
>> +	0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e,
>> 0x20,
>>   	0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900,
>> 0x367, 0x0,
>>   	0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19,
>> 0x0,
>>   	0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0,
>>   	0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
>>   	0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0,
>> 0x0,
>>   	0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff,
>> -	0xc0016900, 0x314, 0x0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
>> +	0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210,
>> 0,
>> +	0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1,
>>   	0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900,
>> 0x20000243, 0x0,
>>   	0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900,
>> 0x24a, 0x0,
>>   	0xc0017900, 0x24b, 0x0
>> @@ -450,7 +451,7 @@ static const uint32_t cached_cmd_gfx9[] = {
>>   	0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0,
>>   	0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020,
>>   	0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf,
>> -	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x12,
>> +	0xc0056900, 0x105, 0x0, 0x0,  0x0, 0x0, 0x1a,
>>   	0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0,
>>   	0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011,
>>   	0xc0026900, 0x292, 0x20, 0x60201b8,
>> @@ -2094,10 +2095,7 @@ static int amdgpu_dispatch_init(uint32_t *ptr,
>> uint32_t ip_type)
>>   	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
>>   	ptr[i++] = 0x204;
>>   	i += 3;
>> -	/* clear mmCOMPUTE_RESOURCE_LIMITS */
>> -	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>> -	ptr[i++] = 0x215;
>> -	ptr[i++] = 0;
>> +
>>   	/* clear mmCOMPUTE_TMPRING_SIZE */
>>   	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>>   	ptr[i++] = 0x218;
>> @@ -2184,6 +2182,7 @@ static void
>> amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>>   					&bo_shader, &ptr_shader,
>>   					&mc_address_shader, &va_shader);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader, 0, bo_shader_size);
>>
>>   	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCLEAR);
>>   	CU_ASSERT_EQUAL(r, 0);
>> @@ -2220,6 +2219,11 @@ static void
>> amdgpu_memset_dispatch_test(amdgpu_device_handle device_handle,
>>   	ptr_cmd[i++] = 0x22222222;
>>   	ptr_cmd[i++] = 0x22222222;
>>
>> +	/* clear mmCOMPUTE_RESOURCE_LIMITS */
>> +	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>> +	ptr_cmd[i++] = 0x215;
>> +	ptr_cmd[i++] = 0;
>> +
>>   	/* dispatch direct command */
>>   	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>>   	ptr_cmd[i++] = 0x10;
>> @@ -2321,6 +2325,7 @@ static void
>> amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>>   					&bo_shader, &ptr_shader,
>>   					&mc_address_shader, &va_shader);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader, 0, bo_shader_size);
>>
>>   	r = amdgpu_dispatch_load_cs_shader(ptr_shader, CS_BUFFERCOPY );
>>   	CU_ASSERT_EQUAL(r, 0);
>> @@ -2365,6 +2370,11 @@ static void
>> amdgpu_memcpy_dispatch_test(amdgpu_device_handle device_handle,
>>   	ptr_cmd[i++] = 0x400;
>>   	ptr_cmd[i++] = 0x74fac;
>>
>> +	/* clear mmCOMPUTE_RESOURCE_LIMITS */
>> +	ptr_cmd[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
>> +	ptr_cmd[i++] = 0x215;
>> +	ptr_cmd[i++] = 0;
>> +
>>   	/* dispatch direct command */
>>   	ptr_cmd[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
>>   	ptr_cmd[i++] = 0x10;
>> @@ -2438,6 +2448,8 @@ static void amdgpu_dispatch_test(void)
>>
>>   	r = amdgpu_query_hw_ip_info(device_handle,
>> AMDGPU_HW_IP_COMPUTE, 0, &info);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	if (!info.available_rings)
>> +		printf("SKIP ... as there's no compute ring\n");
>>
>>   	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>>   		amdgpu_memset_dispatch_test(device_handle,
>> AMDGPU_HW_IP_COMPUTE, ring_id); @@ -2446,6 +2458,8 @@ static void
>> amdgpu_dispatch_test(void)
>>
>>   	r = amdgpu_query_hw_ip_info(device_handle,
>> AMDGPU_HW_IP_GFX, 0, &info);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	if (!info.available_rings)
>> +		printf("SKIP ... as there's no graphics ring\n");
>>
>>   	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>>   		amdgpu_memset_dispatch_test(device_handle,
>> AMDGPU_HW_IP_GFX, ring_id); @@ -2901,12 +2915,14 @@ static void
>> amdgpu_memset_draw_test(amdgpu_device_handle device_handle,
>>   					&bo_shader_ps, &ptr_shader_ps,
>>   					&mc_address_shader_ps,
>> &va_shader_ps);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader_ps, 0, bo_shader_size);
>>
>>   	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size,
>> 4096,
>>   					AMDGPU_GEM_DOMAIN_VRAM, 0,
>>   					&bo_shader_vs, &ptr_shader_vs,
>>   					&mc_address_shader_vs,
>> &va_shader_vs);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader_vs, 0, bo_shader_size);
>>
>>   	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_CONST);
>>   	CU_ASSERT_EQUAL(r, 0);
>> @@ -2996,7 +3012,7 @@ static void
>> amdgpu_memcpy_draw(amdgpu_device_handle device_handle,
>>   	ptr_cmd[i++] = 0x92;
>>   	i += 3;
>>
>> -	ptr_cmd[i++] = PACKET3(PKT3_SET_SH_REG, 1);
>> +	ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1);
>>   	ptr_cmd[i++] = 0x191;
>>   	ptr_cmd[i++] = 0;
>>
>> @@ -3074,12 +3090,14 @@ static void
>> amdgpu_memcpy_draw_test(amdgpu_device_handle device_handle,
>> uint32_t
>>   					&bo_shader_ps, &ptr_shader_ps,
>>   					&mc_address_shader_ps,
>> &va_shader_ps);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader_ps, 0, bo_shader_size);
>>
>>   	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size,
>> 4096,
>>   					AMDGPU_GEM_DOMAIN_VRAM, 0,
>>   					&bo_shader_vs, &ptr_shader_vs,
>>   					&mc_address_shader_vs,
>> &va_shader_vs);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	memset(ptr_shader_vs, 0, bo_shader_size);
>>
>>   	r = amdgpu_draw_load_ps_shader(ptr_shader_ps, PS_TEX);
>>   	CU_ASSERT_EQUAL(r, 0);
>> @@ -3105,6 +3123,8 @@ static void amdgpu_draw_test(void)
>>
>>   	r = amdgpu_query_hw_ip_info(device_handle,
>> AMDGPU_HW_IP_GFX, 0, &info);
>>   	CU_ASSERT_EQUAL(r, 0);
>> +	if (!info.available_rings)
>> +		printf("SKIP ... as there's no graphics ring\n");
>>
>>   	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
>>   		amdgpu_memset_draw_test(device_handle, ring_id);
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

      parent reply	other threads:[~2019-07-19  9:55 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-18  8:10 [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test Cui, Flora
     [not found] ` <1563437433-4157-1-git-send-email-flora.cui-5C7GfCeVMHo@public.gmane.org>
2019-07-18  8:11   ` [PATCH libdrm 2/2] tests/amdgpu: add gpu reset test Cui, Flora
     [not found]     ` <1563437433-4157-2-git-send-email-flora.cui-5C7GfCeVMHo@public.gmane.org>
2019-07-18  9:16       ` Zhang, Hawking
2019-07-18  9:31   ` [PATCH libdrm 1/2] tests/amdgpu: fix for dispatch/draw test Christian König
     [not found]     ` <1c9de651-bbb2-6802-e729-182cab5ca427-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2019-07-19  6:00       ` Cui, Flora
     [not found]         ` <febeaec7-db65-e18d-d073-d7e19f972edb-5C7GfCeVMHo@public.gmane.org>
2019-07-19  7:40           ` Michel Dänzer
     [not found]             ` <39c1c37e-89d8-bb00-2cc6-aa048aed77c8-otUistvHUpPR7s880joybQ@public.gmane.org>
2019-07-19  8:34               ` Cui, Flora
     [not found]                 ` <0a3b4a91-b679-6de3-f02c-5f5a6dfcb82d-5C7GfCeVMHo@public.gmane.org>
2019-07-19  8:40                   ` Michel Dänzer
2019-07-19  7:48   ` Huang, Ray
     [not found]     ` <MN2PR12MB3309C72D7A8B590F848B19FBECCB0-rweVpJHSKTpWdvXm18W95QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2019-07-19  9:55       ` Cui, Flora [this message]

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