From: "Christian König" <christian.koenig@amd.com>
To: John Moore <jbmoore61@gmail.com>
Cc: alexdeucher@gmail.com, alexander.deucher@amd.com,
amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu/gfx: extract compute wptr doorbell helpers to amdgpu_gfx.c
Date: Thu, 30 Apr 2026 15:22:25 +0200 [thread overview]
Message-ID: <acb467cf-0b2d-4733-8df2-23f1ed18b4fd@amd.com> (raw)
In-Reply-To: <CAPUYzBf8EBynRij60SR+EFg1Kn22cyykSOOPxo709bq0xhjpLw@mail.gmail.com>
Hi John,
On 4/30/26 14:32, John Moore wrote:
> Hi Christian,
>
> Thanks for the review. All points addressed below.
>
>> That should probably be readq() instead of this horrible and not
>> portable cast to atomic64_t.
>>
>> Alternatively we could just normally read the pointer with a memory
>> barrier since this is just system memory.
>
> I went with the second option — this is system memory (writeback via
> GTT), not MMIO, so readq() felt semantically wrong. The v2 uses:
>
> get: wptr = READ_ONCE(*(u64 *)ring->wptr_cpu_addr);
> smp_rmb();
This needs to be rmb() and not smp_rmb(); smp_rmb() is only for CPU<->CPU synchronization but here we need CPU<->device synchronization.
And it needs to come *before* the read!
>
> set: WRITE_ONCE(*(u64 *)ring->wptr_cpu_addr, ring->wptr);
> smp_wmb();
Same here, but this time least the barrier ordering is correct.
> WDOORBELL64(ring->doorbell_index, ring->wptr);
>
> The alignment is safe — amdgpu_device_wb_get() returns offsets in
> multiples of 8 dwords (32 bytes), so the u64* cast always lands on
> a naturally-aligned address.
>
> One question: READ_ONCE on a u64 is not atomic on 32-bit
> architectures (unlike atomic64_read which uses cmpxchg8b). DRM_AMDGPU
> has no formal CONFIG_64BIT dependency in Kconfig, though in practice
> nobody runs it on 32-bit.
We still have some people trying to use it on 32bit kernels. We should maybe consider to drop the 32bit support.
> Is READ_ONCE acceptable here, or would you
> prefer readq() to keep the atomicity guarantee?
Yeah good question I don't really know what to do here.
On the one hand you are right, writeq()/readq() are not correct because this isn't MMIO but system memory.
On the other hand I don't think Linux has an architecture independent way to guarantee that a write to system memory is done as an atomic 64bit write.
What we need to guarantee is that the device never sees an incomplete value because the write is done as two 32bit writes. That is probably the reason why we used the atomic64_t hack in the first place.
Regards,
Christian.
>
>> Pre-requisite/error checking first please.
>> Make that a if (WARN_ON(!ring->use_doorbell)) return.
>
> Done. Both functions now have the guard at the top:
>
> if (WARN_ON(!ring->use_doorbell))
> return 0; /* or return; for set_wptr */
>
>> And please don't use WARN_ON_ONCE() that is just to reduce the
>> amount of warnings printed into the logs on real HW errors.
>>
>> On functional coding errors like this one here it doesn't make sense
>> and is often overlooked.
>
> Understood — changed to WARN_ON.
>
>> Same here the case to atomic64_t is extremely questionable.
>
> Fixed in set_wptr as well, same READ_ONCE/WRITE_ONCE approach.
>
> v2 incoming once I hear back on the readq vs READ_ONCE question.
>
> Thanks,
> John
>
> "I will not be pushed, filed, stamped, indexed, briefed, debriefed, or numbered."
> ~ The Prisoner
>
>
>
>
> On Thu, Apr 30, 2026 at 2:19 AM Christian König <christian.koenig@amd.com <mailto:christian.koenig@amd.com>> wrote:
>
> On 4/29/26 22:20, John B. Moore wrote:
> > Move the duplicated doorbell-based get_wptr/set_wptr functions from
> > gfx_v9_0.c, gfx_v10_0.c, gfx_v11_0.c, and gfx_v12_0.c into common
> > helpers amdgpu_gfx_get_wptr_compute() and amdgpu_gfx_set_wptr_compute()
> > in amdgpu_gfx.c.
> >
> > These functions are not HW generation dependent -- the doorbell path is
> > identical across all four GFX versions:
> >
> > get: atomic64_read(ring->wptr_cpu_addr)
> > set: atomic64_set(ring->wptr_cpu_addr) + WDOORBELL64()
> >
> > The non-doorbell fallback is replaced with WARN_ON_ONCE instead of BUG()
> > since doorbell is the only supported method on gfx9+ compute rings.
> >
> > Not touched: gfx_v7_0, gfx_v8_0, gfx_v9_4_3 -- these have different
> > wptr access patterns (MMIO registers or wb.wb[] offsets).
> >
> > Suggested-by: Alex Deucher <alexander.deucher@amd.com <mailto:alexander.deucher@amd.com>>
> > Signed-off-by: John Moore <jbmoore61@gmail.com <mailto:jbmoore61@gmail.com>>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 39 +++++++++++++++++++++++++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 ++
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 33 +++------------------
> > drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 34 +++------------------
> > drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 34 +++------------------
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 39 +++----------------------
> > 6 files changed, 58 insertions(+), 124 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > index 77578ecc6..9e9c5cb81 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> > @@ -2596,3 +2596,42 @@ void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev)
> > #endif
> > }
> >
> > +/**
> > + * amdgpu_gfx_get_wptr_compute - common get_wptr for compute rings using doorbells
> > + * @ring: amdgpu_ring pointer
> > + *
> > + * Read the write pointer from the doorbell-mapped writeback address.
> > + * This is HW-agnostic and shared across GFX generations that use
> > + * doorbell-based compute queue management.
> > + */
> > +u64 amdgpu_gfx_get_wptr_compute(struct amdgpu_ring *ring)
> > +{
> > + /* XXX check if swapping is necessary on BE */
> > + if (ring->use_doorbell)
> > + return atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
>
> That should probably be readq() instead of this horrible and not portable cast to atomic64_t.
>
> Alternatively we could just normally read the pointer with a memory barrier since this is just system memory.
>
> > +
> > + WARN_ON_ONCE(1);
>
> Pre-requisite/error checking first please.
>
> Make that a if (WARN_ON(!ring->use_doorbell)) return.
>
> And please don't use WARN_ON_ONCE() that is just to reduce the amount of warnings printed into the logs on real HW errors.
>
> On functional coding errors like this one here it doesn't make sense and is often overlooked.
>
> > + return 0;
> > +}
> > +
> > +/**
> > + * amdgpu_gfx_set_wptr_compute - common set_wptr for compute rings using doorbells
> > + * @ring: amdgpu_ring pointer
> > + *
> > + * Write the write pointer to the doorbell-mapped writeback address and
> > + * ring the doorbell. This is HW-agnostic and shared across GFX
> > + * generations that use doorbell-based compute queue management.
> > + */
> > +void amdgpu_gfx_set_wptr_compute(struct amdgpu_ring *ring)
> > +{
> > + struct amdgpu_device *adev = ring->adev;
> > +
> > + /* XXX check if swapping is necessary on BE */
> > + if (ring->use_doorbell) {
> > + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
>
> Same here the case to atomic64_t is extremely questionable.
>
> Regards,
> Christian.
>
> > + WDOORBELL64(ring->doorbell_index, ring->wptr);
> > + } else {
> > + WARN_ON_ONCE(1);
> > + }
> > +}
> > +
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > index 585cc8e81..27f6beafb 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
> > @@ -653,6 +653,9 @@ u32 amdgpu_gfx_csb_preamble_start(u32 *buffer);
> > u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count);
> > void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count);
> >
> > +u64 amdgpu_gfx_get_wptr_compute(struct amdgpu_ring *ring);
> > +void amdgpu_gfx_set_wptr_compute(struct amdgpu_ring *ring);
> > +
> > void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev);
> > void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev);
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 1893ceeeb..4c0272cba 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -8586,31 +8586,6 @@ static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
> > return *(uint32_t *)ring->rptr_cpu_addr;
> > }
> >
> > -static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> > -{
> > - u64 wptr;
> > -
> > - /* XXX check if swapping is necessary on BE */
> > - if (ring->use_doorbell)
> > - wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
> > - else
> > - BUG();
> > - return wptr;
> > -}
> > -
> > -static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
> > -{
> > - struct amdgpu_device *adev = ring->adev;
> > -
> > - if (ring->use_doorbell) {
> > - atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
> > - ring->wptr);
> > - WDOORBELL64(ring->doorbell_index, ring->wptr);
> > - } else {
> > - BUG(); /* only DOORBELL method supported on gfx10 now */
> > - }
> > -}
> > -
> > static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> > {
> > struct amdgpu_device *adev = ring->adev;
> > @@ -9881,8 +9856,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
> > .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> > .support_64bit_ptrs = true,
> > .get_rptr = gfx_v10_0_ring_get_rptr_compute,
> > - .get_wptr = gfx_v10_0_ring_get_wptr_compute,
> > - .set_wptr = gfx_v10_0_ring_set_wptr_compute,
> > + .get_wptr = amdgpu_gfx_get_wptr_compute,
> > + .set_wptr = amdgpu_gfx_set_wptr_compute,
> > .emit_frame_size =
> > 20 + /* gfx_v10_0_ring_emit_gds_switch */
> > 7 + /* gfx_v10_0_ring_emit_hdp_flush */
> > @@ -9921,8 +9896,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
> > .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> > .support_64bit_ptrs = true,
> > .get_rptr = gfx_v10_0_ring_get_rptr_compute,
> > - .get_wptr = gfx_v10_0_ring_get_wptr_compute,
> > - .set_wptr = gfx_v10_0_ring_set_wptr_compute,
> > + .get_wptr = amdgpu_gfx_get_wptr_compute,
> > + .set_wptr = amdgpu_gfx_set_wptr_compute,
> > .emit_frame_size =
> > 20 + /* gfx_v10_0_ring_emit_gds_switch */
> > 7 + /* gfx_v10_0_ring_emit_hdp_flush */
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > index 427975b5a..404604f2d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> > @@ -5818,32 +5818,6 @@ static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
> > return *(uint32_t *)ring->rptr_cpu_addr;
> > }
> >
> > -static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> > -{
> > - u64 wptr;
> > -
> > - /* XXX check if swapping is necessary on BE */
> > - if (ring->use_doorbell)
> > - wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
> > - else
> > - BUG();
> > - return wptr;
> > -}
> > -
> > -static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
> > -{
> > - struct amdgpu_device *adev = ring->adev;
> > -
> > - /* XXX check if swapping is necessary on BE */
> > - if (ring->use_doorbell) {
> > - atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
> > - ring->wptr);
> > - WDOORBELL64(ring->doorbell_index, ring->wptr);
> > - } else {
> > - BUG(); /* only DOORBELL method supported on gfx11 now */
> > - }
> > -}
> > -
> > static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> > {
> > struct amdgpu_device *adev = ring->adev;
> > @@ -7266,8 +7240,8 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
> > .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> > .support_64bit_ptrs = true,
> > .get_rptr = gfx_v11_0_ring_get_rptr_compute,
> > - .get_wptr = gfx_v11_0_ring_get_wptr_compute,
> > - .set_wptr = gfx_v11_0_ring_set_wptr_compute,
> > + .get_wptr = amdgpu_gfx_get_wptr_compute,
> > + .set_wptr = amdgpu_gfx_set_wptr_compute,
> > .emit_frame_size =
> > 5 + /* update_spm_vmid */
> > 20 + /* gfx_v11_0_ring_emit_gds_switch */
> > @@ -7307,8 +7281,8 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
> > .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> > .support_64bit_ptrs = true,
> > .get_rptr = gfx_v11_0_ring_get_rptr_compute,
> > - .get_wptr = gfx_v11_0_ring_get_wptr_compute,
> > - .set_wptr = gfx_v11_0_ring_set_wptr_compute,
> > + .get_wptr = amdgpu_gfx_get_wptr_compute,
> > + .set_wptr = amdgpu_gfx_set_wptr_compute,
> > .emit_frame_size =
> > 20 + /* gfx_v11_0_ring_emit_gds_switch */
> > 7 + /* gfx_v11_0_ring_emit_hdp_flush */
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> > index 79ea1af36..7ba436444 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
> > @@ -4363,32 +4363,6 @@ static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
> > return *(uint32_t *)ring->rptr_cpu_addr;
> > }
> >
> > -static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> > -{
> > - u64 wptr;
> > -
> > - /* XXX check if swapping is necessary on BE */
> > - if (ring->use_doorbell)
> > - wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
> > - else
> > - BUG();
> > - return wptr;
> > -}
> > -
> > -static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
> > -{
> > - struct amdgpu_device *adev = ring->adev;
> > -
> > - /* XXX check if swapping is necessary on BE */
> > - if (ring->use_doorbell) {
> > - atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
> > - ring->wptr);
> > - WDOORBELL64(ring->doorbell_index, ring->wptr);
> > - } else {
> > - BUG(); /* only DOORBELL method supported on gfx12 now */
> > - }
> > -}
> > -
> > static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
> > {
> > struct amdgpu_device *adev = ring->adev;
> > @@ -5523,8 +5497,8 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
> > .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> > .support_64bit_ptrs = true,
> > .get_rptr = gfx_v12_0_ring_get_rptr_compute,
> > - .get_wptr = gfx_v12_0_ring_get_wptr_compute,
> > - .set_wptr = gfx_v12_0_ring_set_wptr_compute,
> > + .get_wptr = amdgpu_gfx_get_wptr_compute,
> > + .set_wptr = amdgpu_gfx_set_wptr_compute,
> > .emit_frame_size =
> > 7 + /* gfx_v12_0_ring_emit_hdp_flush */
> > 5 + /* hdp invalidate */
> > @@ -5561,8 +5535,8 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {
> > .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> > .support_64bit_ptrs = true,
> > .get_rptr = gfx_v12_0_ring_get_rptr_compute,
> > - .get_wptr = gfx_v12_0_ring_get_wptr_compute,
> > - .set_wptr = gfx_v12_0_ring_set_wptr_compute,
> > + .get_wptr = amdgpu_gfx_get_wptr_compute,
> > + .set_wptr = amdgpu_gfx_set_wptr_compute,
> > .emit_frame_size =
> > 7 + /* gfx_v12_0_ring_emit_hdp_flush */
> > 5 + /*hdp invalidate */
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 8249135d7..798f94bca 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -5640,37 +5640,6 @@ static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
> > return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */
> > }
> >
> > -static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
> > -{
> > - u64 wptr;
> > -
> > - /* XXX check if swapping is necessary on BE */
> > - if (ring->use_doorbell) {
> > - wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
> > - } else {
> > - WARN_ONCE(1, "gfx_v9_0: non-doorbell wptr read on ring %s, "
> > - "only doorbell method supported on gfx9\n",
> > - ring->name);
> > - wptr = 0;
> > - }
> > - return wptr;
> > -}
> > -
> > -static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
> > -{
> > - struct amdgpu_device *adev = ring->adev;
> > -
> > - /* XXX check if swapping is necessary on BE */
> > - if (ring->use_doorbell) {
> > - atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
> > - WDOORBELL64(ring->doorbell_index, ring->wptr);
> > - } else {
> > - WARN_ONCE(1, "gfx_v9_0: non-doorbell wptr write on ring %s, "
> > - "only doorbell method supported on gfx9\n",
> > - ring->name);
> > - }
> > -}
> > -
> > static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
> > u64 seq, unsigned int flags)
> > {
> > @@ -7627,8 +7596,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
> > .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> > .support_64bit_ptrs = true,
> > .get_rptr = gfx_v9_0_ring_get_rptr_compute,
> > - .get_wptr = gfx_v9_0_ring_get_wptr_compute,
> > - .set_wptr = gfx_v9_0_ring_set_wptr_compute,
> > + .get_wptr = amdgpu_gfx_get_wptr_compute,
> > + .set_wptr = amdgpu_gfx_set_wptr_compute,
> > .emit_frame_size =
> > 20 + /* gfx_v9_0_ring_emit_gds_switch */
> > 7 + /* gfx_v9_0_ring_emit_hdp_flush */
> > @@ -7669,8 +7638,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
> > .nop = PACKET3(PACKET3_NOP, 0x3FFF),
> > .support_64bit_ptrs = true,
> > .get_rptr = gfx_v9_0_ring_get_rptr_compute,
> > - .get_wptr = gfx_v9_0_ring_get_wptr_compute,
> > - .set_wptr = gfx_v9_0_ring_set_wptr_compute,
> > + .get_wptr = amdgpu_gfx_get_wptr_compute,
> > + .set_wptr = amdgpu_gfx_set_wptr_compute,
> > .emit_frame_size =
> > 20 + /* gfx_v9_0_ring_emit_gds_switch */
> > 7 + /* gfx_v9_0_ring_emit_hdp_flush */
>
next prev parent reply other threads:[~2026-04-30 13:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-29 20:20 [PATCH] drm/amdgpu/gfx: extract compute wptr doorbell helpers to amdgpu_gfx.c John B. Moore
2026-04-29 20:29 ` Alex Deucher
2026-04-30 7:19 ` Christian König
2026-04-30 12:32 ` John Moore
2026-04-30 13:22 ` Christian König [this message]
2026-04-30 13:26 ` Alex Deucher
2026-04-30 13:49 ` Christian König
2026-04-30 13:57 ` John Moore
-- strict thread matches above, loose matches on Subject: below --
2026-04-29 20:25 John B. Moore
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