[bug report] drm/amd/display: Fix dml2_0 narrowing boundaries

[Dan Carpenter <error27@gmail.com>]

Hello Gaghik Khachatrian,

Commit 11236ac905e7 ("drm/amd/display: Fix dml2_0 narrowing
boundaries") from Apr 9, 2026 (linux-next), leads to the following
Smatch static checker warning:

	drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_mall_phantom.c:601 subvp_vblank_schedulable()
	warn: unsigned subtraction: 'subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion' use '!='

drivers/gpu/drm/amd/amdgpu/../display/dc/dml2_0/dml2_mall_phantom.c
    521 static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *context)
    522 {
    523         struct pipe_ctx *pipe = NULL;
    524         struct pipe_ctx *subvp_pipe = NULL;
    525         bool found = false;
    526         bool schedulable = false;
    527         uint32_t i = 0;
    528         uint8_t vblank_index = 0;
    529         uint32_t prefetch_us = 0;
    530         uint32_t mall_region_us = 0;
    531         uint32_t vblank_frame_us = 0;
    532         uint32_t subvp_active_us = 0;
    533         uint32_t vblank_blank_us = 0;

Originally these were u16 but the commit changed them to u32.

    534         uint32_t max_vblank_mallregion = 0;
    535         struct dc_crtc_timing *main_timing = NULL;
    536         struct dc_crtc_timing *phantom_timing = NULL;
    537         struct dc_crtc_timing *vblank_timing = NULL;
    538         struct dc_stream_state *phantom_stream;
    539         enum mall_stream_type pipe_mall_type;
    540 
    541         /* For SubVP + VBLANK/DRR cases, we assume there can only be
    542          * a single VBLANK/DRR display. If DML outputs SubVP + VBLANK
    543          * is supported, it is either a single VBLANK case or two VBLANK

[ snip ]

    573         // Use ignore_msa_timing_param flag to identify as DRR
    574         if (found && context->res_ctx.pipe_ctx[vblank_index].stream->ignore_msa_timing_param) {
    575                 // SUBVP + DRR case
    576                 schedulable = dml2_svp_drr_schedulable(ctx, context, &context->res_ctx.pipe_ctx[vblank_index].stream->timing);
    577         } else if (found) {
    578                 phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, subvp_pipe->stream);
    579                 main_timing = &subvp_pipe->stream->timing;
    580                 phantom_timing = &phantom_stream->timing;
    581                 vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
    582                 // Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
    583                 // Also include the prefetch end to mallstart delay time
    584                 prefetch_us = (uint32_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
    585                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
    586                                 ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us);
    587                 // P-State allow width and FW delays already included phantom_timing->v_addressable
    588                 mall_region_us = (uint32_t)(phantom_timing->v_addressable * phantom_timing->h_total /
    589                                 (double)(phantom_timing->pix_clk_100hz * 100) * 1000000);
    590                 vblank_frame_us = (uint32_t)(vblank_timing->v_total * vblank_timing->h_total /
    591                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000);
    592                 vblank_blank_us = (uint32_t)((vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
    593                                 (double)(vblank_timing->pix_clk_100hz * 100) * 1000000);
    594                 subvp_active_us = (uint32_t)(main_timing->v_addressable * main_timing->h_total /
    595                                 (double)(main_timing->pix_clk_100hz * 100) * 1000000);
    596                 max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
    597 
    598                 // Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
    599                 // and the max of (VBLANK blanking time, MALL region)
    600                 // TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
--> 601                 if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)

With u16 types this was type promoted to int so the result could be
negative, but now it's u32 and the result can never be negative.


    602                         schedulable = true;
    603         }
    604         return schedulable;
    605 }

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regards,
dan carpenter