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[95.117.118.122]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3ebc3dcbsm19591505f8f.14.2026.10.26.19.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 19:16:07 -0700 (PDT) Date: Tue, 27 Oct 2026 03:15:34 +0100 From: Karl Mehltretter To: Alistair Popple Cc: dri-devel@lists.freedesktop.org, christian.koenig@amd.com, sumit.semwal@linaro.org, jgg@nvidia.com, Thomas =?utf-8?Q?Hellstr=C3=B6m?= , Simona Vetter , Matthew Brost , Vivek Kasireddy , Dongwon Kim , Leon Romanovsky , Kevin Tian , Xu Yilun , Baolu Lu , Felix Kuehling , Alex Deucher , intel-xe@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org, linux-rdma@vger.kernel.org, iommu@lists.linux.dev, Alexey Kardashevskiy , zhipingz@meta.com, treding@nvidia.com, jhubbard@nvidia.com Subject: Re: [PATCH 23/26] treewide: Rename dma_buf_attach() to dma_buf_sgt_attach() Message-ID: References: <20261026053623.202642-1-apopple@nvidia.com> <20261026053623.202642-24-apopple@nvidia.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261026053623.202642-24-apopple@nvidia.com> X-Mailman-Approved-At: Tue, 27 Oct 2026 09:34:11 +0000 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-6.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FORGED_GMAIL_RCVD,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Mon, Oct 26, 2026 at 04:36:14PM +0100, Alistair Popple wrote: Testing the series on a Jetson Nano exposed this path. A 3 MiB system-heap buffer was imported into Tegra DRM and scanned out over HDMI. With CONFIG_DMABUF_DEBUG=y the PRIME import succeeded, but scanout immediately produced display SMMU faults starting at 0x300000. Tracing the fault led here: > @@ -475,7 +475,7 @@ static struct tegra_bo *tegra_bo_import(struct drm_device *drm, > * domain, map it first to the DRM device to get an sgt. > */ > if (tegra->domain) { > - attach = dma_buf_attach(buf, drm->dev); > + attach = dma_buf_sgt_attach(buf, drm->dev); tegra_bo_import() passes the attachment SGT to iommu_map_sgtable(), which uses sg_phys() and sg->length. The SGT mapping contract only guarantees the DMA address and length fields. The debug wrapper clears the page-side fields, so iommu_map_sgtable() maps zero bytes. Tegra only treats negative returns as errors and keeps the reserved IOVA, which scanout then faults on. This page-side use predates the series, so the fault is not itself a v2 regression. Is dma_buf_sgt_attach() valid for this call site, or does Tegra need a page/physical mapping type first? Karl