From: Paul Menzel <pmenzel@molgen.mpg.de>
To: Alex Deucher <alexander.deucher@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>,
it+linux-iommu@molgen.mpg.de,
Alex Deucher <alexdeucher@gmail.com>
Subject: Re: [PATCH] drm/amdgpu/gmc6: fix DMA mask
Date: Thu, 28 Oct 2021 10:32:59 +0200 [thread overview]
Message-ID: <b1b2b722-d21e-421a-e8b1-5452d404533d@molgen.mpg.de> (raw)
In-Reply-To: <a0801433-fd70-f15d-3f63-7ca18fbf2244@molgen.mpg.de>
Dear Alex,
On 28.10.21 00:19, Paul Menzel wrote:
> On 27.10.21 20:23, Alex Deucher wrote:
>> On Wed, Oct 27, 2021 at 2:22 PM Alex Deucher
>> <alexander.deucher@amd.com> wrote:
>>>
>>> The DMA mask on SI parts is 40 bits not 44. Looks like a copy
>>> paste typo.
>>
>> Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1762
>>
>> Fixed locally.
>
> As I have no way to reproduce this, as the ring gfx timeout error is
> logged ten seconds after the IO_PAGE_FAULT, is very likely to be related?
>
> Hopefully I am going to be able to test this on Friday. Does AMD’s QA
> team have the cards to test the `iommu.forcedac=1` case? Is that test
> case going to be added to the “test protocol”?
>
> Lastly, should a Fixes tag be added, so it’s picked up for the stable
> series?
Does the value of 44 need to be changed to 40 also five lines below?
- adev->need_swiotlb = drm_need_swiotlb(44);
+ adev->need_swiotlb = drm_need_swiotlb(40);
Kind regards,
Paul
next prev parent reply other threads:[~2021-10-28 8:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-27 18:22 [PATCH] drm/amdgpu/gmc6: fix DMA mask Alex Deucher
2021-10-27 18:23 ` Alex Deucher
2021-10-27 22:19 ` Paul Menzel
2021-10-28 8:32 ` Paul Menzel [this message]
2021-10-28 10:06 ` Paul Menzel
2021-10-28 14:14 ` Alex Deucher
2021-10-28 7:07 ` Christian König
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