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Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Broadworth , chiahsuan.chung@amd.com, Sunpeng.Li@amd.com, Rodrigo.Siqueira@amd.com, jerry.zuo@amd.com, hamza.mahfooz@amd.com, wayne.lin@amd.com, Harry.Wentland@amd.com Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 1/24/2024 11:09, Roman.Li@amd.com wrote: > From: Roman Li > > [Why] > While in IPS2 an access to dcn registers is not allowed. > If interrupt results in dc call, we should disable IPS. > > [How] > Safeguard register access in IPS2 by disabling idle optimization > before calling dc interrupt setting api. > > Signed-off-by: Roman Li > Tested-by: Mark Broadworth Reviewed-by: Mario Limonciello > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c > index 58b880acb087..3390f0d8420a 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c > @@ -711,7 +711,7 @@ static inline int dm_irq_state(struct amdgpu_device *adev, > { > bool st; > enum dc_irq_source irq_source; > - > + struct dc *dc = adev->dm.dc; > struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id]; > > if (!acrtc) { > @@ -729,6 +729,9 @@ static inline int dm_irq_state(struct amdgpu_device *adev, > > st = (state == AMDGPU_IRQ_STATE_ENABLE); > > + if (dc && dc->caps.ips_support && dc->idle_optimizations_allowed) > + dc_allow_idle_optimizations(dc, false); > + > dc_interrupt_set(adev->dm.dc, irq_source, st); > return 0; > }