* [PATCH v2 0/5] Expand kernel-doc with more generic details and info about ring buffers
@ 2025-08-24 23:29 Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
` (4 more replies)
0 siblings, 5 replies; 19+ messages in thread
From: Rodrigo Siqueira @ 2025-08-24 23:29 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
Lately, I have been part of multiple discussions around GPU recovery and
other concepts associated with GFX/Compute. Most of the debate is spread
around GitLab issues, emails, and some meeting conversations. This
patchset aims to consolidate all that information into a single
kernel-doc, which can be collaboratively improved and shared with other
people.
In this series, you will find new amdgpu glossary entries, more details
about the IPs' interconnections, and a description of the ring buffer.
This series includes multiple SVG diagrams; for this reason, it might be
good to apply this series locally.
Finally, keep in mind that I tried to fill in some gaps between
information, and hopefully, my description matches the reality.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Changes since V1:
- Patch 1: Shorten the function description.
- Patch 4: Add more details about CPF, CPC, CPG, MEC, PFP, and ME.
Thanks
Rodrigo Siqueira (5):
drm/amdgpu: Expand kernel-doc in amdgpu_ring
Documentation/gpu: Add new glossary entries from UMR
Documentation/gpu: Expand generic block information
Documentation/gpu: Add more information about GC
Documentation/gpu: Add documentation about ring buffer
.../gpu/amdgpu/amd_overview_block.svg | 674 +++++++
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 24 +
Documentation/gpu/amdgpu/driver-core.rst | 25 +
.../gpu/amdgpu/enforce_isolation.svg | 707 +++++++
Documentation/gpu/amdgpu/gc/cu.svg | 437 +++++
Documentation/gpu/amdgpu/gc/index.rst | 32 +-
Documentation/gpu/amdgpu/gfx_pipeline_seq.svg | 413 +++++
Documentation/gpu/amdgpu/index.rst | 1 +
.../gpu/amdgpu/no_enforce_isolation.svg | 673 +++++++
Documentation/gpu/amdgpu/ring-buffer.rst | 94 +
Documentation/gpu/amdgpu/ring_buffers.svg | 1633 +++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 14 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 +
13 files changed, 4720 insertions(+), 9 deletions(-)
create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/gc/cu.svg
create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg
--
2.47.2
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring
2025-08-24 23:29 [PATCH v2 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
@ 2025-08-24 23:29 ` Rodrigo Siqueira
2025-08-25 15:19 ` Christian König
2025-08-24 23:29 ` [PATCH v2 2/5] Documentation/gpu: Add new glossary entries from UMR Rodrigo Siqueira
` (3 subsequent siblings)
4 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Siqueira @ 2025-08-24 23:29 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
Expand the kernel-doc about amdgpu_ring and add some tiny improvements.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 14 +++++++++++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 6379bb25bf5c..80dd6f58a53b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -75,8 +75,15 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
* @ring: amdgpu_ring structure holding ring information
* @ndw: number of dwords to allocate in the ring buffer
*
- * Allocate @ndw dwords in the ring buffer (all asics).
- * Returns 0 on success, error on failure.
+ * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When
+ * inspecting the code, you may encounter places where this function is called
+ * amdgpu_ring_alloc(ring, X + Y + Z), where X, Y, and Z are integer numbers.
+ * This indicates the number of dword operations to be inserted into the ring
+ * per operation.
+ *
+ * Returns:
+ * 0 on success, otherwise -ENOMEM if it tries to allocate more than the
+ * maximum dword allowed for one submission.
*/
int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
{
@@ -122,7 +129,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
ring->funcs->begin_use(ring);
}
-/** amdgpu_ring_insert_nop - insert NOP packets
+/**
+ * amdgpu_ring_insert_nop - insert NOP packets
*
* @ring: amdgpu_ring structure holding ring information
* @count: the number of NOP packets to insert
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 7670f5d82b9e..d27dbb3c109f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
#define AMDGPU_FENCE_FLAG_INT (1 << 1)
#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
+
+/* Ensure the execution in case of preemption or reset */
#define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
--
2.47.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 2/5] Documentation/gpu: Add new glossary entries from UMR
2025-08-24 23:29 [PATCH v2 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
@ 2025-08-24 23:29 ` Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 3/5] Documentation/gpu: Expand generic block information Rodrigo Siqueira
` (2 subsequent siblings)
4 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Siqueira @ 2025-08-24 23:29 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
When using UMR, a dashboard is available that displays the CPC, CPF,
CPG, TCP, and UTCL utilization. This commit introduces the meanings of
those acronyms (and others) to the glossary to improve the comprehension
of the UMR dashboard.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 21 ++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index 30812d9d53c6..eb72e6f6d4f1 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -30,6 +30,15 @@ we have a dedicated glossary for Display Core at
CP
Command Processor
+ CPC
+ Command Processor Compute
+
+ CPF
+ Command Processor Fetch
+
+ CPG
+ Command Processor Graphics
+
CPLIB
Content Protection Library
@@ -78,6 +87,9 @@ we have a dedicated glossary for Display Core at
GMC
Graphic Memory Controller
+ GPR
+ General Purpose Register
+
GPUVM
GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple
virtual address spaces that can be in flight at any given time. These
@@ -92,6 +104,9 @@ we have a dedicated glossary for Display Core at
table for use by the kernel driver or into per process GPUVM page tables
for application usage.
+ GWS
+ Global Wave Syncs
+
IH
Interrupt Handler
@@ -206,12 +221,18 @@ we have a dedicated glossary for Display Core at
TC
Texture Cache
+ TCP (AMDGPU)
+ Texture Cache Processing
+
TOC
Table of Contents
UMSCH
User Mode Scheduler
+ UTCL
+ Universal Texture Cache Line
+
UVD
Unified Video Decoder
--
2.47.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 3/5] Documentation/gpu: Expand generic block information
2025-08-24 23:29 [PATCH v2 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 2/5] Documentation/gpu: Add new glossary entries from UMR Rodrigo Siqueira
@ 2025-08-24 23:29 ` Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 4/5] Documentation/gpu: Add more information about GC Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 5/5] Documentation/gpu: Add documentation about ring buffer Rodrigo Siqueira
4 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Siqueira @ 2025-08-24 23:29 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
This commit expands the overall explanation about AMD GPU IPs by adding
more details about their interconnection. Note that this commit includes
a diagram that provides additional information.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
.../gpu/amdgpu/amd_overview_block.svg | 674 ++++++++++++++++++
Documentation/gpu/amdgpu/amdgpu-glossary.rst | 3 +
Documentation/gpu/amdgpu/driver-core.rst | 25 +
3 files changed, 702 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg
diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
new file mode 100644
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diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index eb72e6f6d4f1..a3f9565d655b 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at
TOC
Table of Contents
+ UMC
+ Unified Memory Controller
+
UMSCH
User Mode Scheduler
diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
index 81256318e93c..f47199c04d8f 100644
--- a/Documentation/gpu/amdgpu/driver-core.rst
+++ b/Documentation/gpu/amdgpu/driver-core.rst
@@ -77,6 +77,31 @@ VCN (Video Core Next)
decode. It's exposed to userspace for user mode drivers (VA-API,
OpenMAX, etc.)
+It is important to note that these blocks can interact with each other. The
+picture below illustrates some of the components and their interconnection:
+
+.. kernel-figure:: amd_overview_block.svg
+
+In the diagram, memory-related blocks are represented by a green color. Notice
+that specific IPs have a green block that represents a small hardware block
+named 'hub', which is responsible for interfacing with memory (pre-vega devices
+have a dedicated block for that, named GMC). In the driver code, you can
+identify this component by looking for the suffix hub, for example: gfxhub,
+dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in
+turn is connected to memory blocks.
+
+There is some level of protection for certain elements in memory, and the PSP
+plays an essential role in this area. For example, when a specific firmware is
+loaded into the memory, PSP takes an action to ensure that the firmware has a
+valid signature. Another use of PSP is to support the TA (e.g., HDCP) and
+encrypted memory via TMZ.
+
+Another IP that deserves attention is the SMU, as it is connected to all the
+other IPs. SMU will help put the GPU in optimal utilization by taking into
+account performance and power consumption. SMU helps other blocks to set up a
+proper clock configuration. Another feature of SMU is the support for resetting
+every component.
+
.. _pipes-and-queues-description:
GFX, Compute, and SDMA Overall Behavior
--
2.47.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-24 23:29 [PATCH v2 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
` (2 preceding siblings ...)
2025-08-24 23:29 ` [PATCH v2 3/5] Documentation/gpu: Expand generic block information Rodrigo Siqueira
@ 2025-08-24 23:29 ` Rodrigo Siqueira
2025-08-25 15:38 ` Alex Deucher
2025-08-24 23:29 ` [PATCH v2 5/5] Documentation/gpu: Add documentation about ring buffer Rodrigo Siqueira
4 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Siqueira @ 2025-08-24 23:29 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
This commit introduces a diagram and a set of information that details
the different sets of schedulers available in the SE.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
Documentation/gpu/amdgpu/gc/cu.svg | 437 ++++++++++++++++++++++++++
Documentation/gpu/amdgpu/gc/index.rst | 32 +-
2 files changed, 463 insertions(+), 6 deletions(-)
create mode 100644 Documentation/gpu/amdgpu/gc/cu.svg
diff --git a/Documentation/gpu/amdgpu/gc/cu.svg b/Documentation/gpu/amdgpu/gc/cu.svg
new file mode 100644
index 000000000000..10bdb3e24b65
--- /dev/null
+++ b/Documentation/gpu/amdgpu/gc/cu.svg
@@ -0,0 +1,437 @@
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diff --git a/Documentation/gpu/amdgpu/gc/index.rst b/Documentation/gpu/amdgpu/gc/index.rst
index ff6e9ef5cbee..19f2ba53ee49 100644
--- a/Documentation/gpu/amdgpu/gc/index.rst
+++ b/Documentation/gpu/amdgpu/gc/index.rst
@@ -10,16 +10,36 @@ producer-consumer problem, where the CPU fills out a buffer with operations
the buffer are called Command Packets, which can be summarized as a compressed
way of transmitting command information to the graphics controller.
+In the diagram below, you can see an overview of the GC, along with additional
+information about the Shader Engine (SE).
+
+.. kernel-figure:: cu.svg
+
+First of all, note that the GC can have multiple SEs, depending on the specific
+GPU/APU, and each SE has multiple Compute Units (CU). From the diagram, you can
+see that CUs have a block named Schedulers. The reason the name is in plural is
+because this hardware block is a combination of different micro-schedules: CP,
+CPF, CPC, and CPG.
+
The component that acts as the front end between the CPU and the GPU is called
-the Command Processor (CP). This component is responsible for providing greater
+CP (Command Processor). This component is responsible for providing greater
flexibility to the GC since CP makes it possible to program various aspects of
the GPU pipeline. CP also coordinates the communication between the CPU and GPU
via a mechanism named **Ring Buffers**, where the CPU appends information to
-the buffer while the GPU removes operations. It is relevant to highlight that a
-CPU can add a pointer to the Ring Buffer that points to another region of
-memory outside the Ring Buffer, and CP can handle it; this mechanism is called
-**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
-writes the operations to the correct hardware blocks.
+the buffer while the GPU removes operations. Finally, CP is also responsible
+for handling Indirect Buffers (IB).
+
+After CP completes the first set of processing, which includes separate command
+packets specific to GFX and Compute, other blocks step in. To handle commands
+for the compute block, CPC (Command Processor Command) takes over, and for
+handling Graphics operations, the CPG (Command Processor Graphics) takes
+action. Another essential block to ensure the optimal utilization of CPC and
+CPG is the CPF (Command Processor Fetcher), which helps these blocks to be
+constantly fed. Note that CPG contains the PFP (Pre-Fetch Parser), ME
+(MicroEngine), and CE (Constant Engine) in the case of chips that support it.
+CPC contains MEC (MicroEngine Compute), and CPF is another hardware block that
+provides services to CPG and CPC.
+
Graphics (GFX) and Compute Microcontrollers
-------------------------------------------
--
2.47.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 5/5] Documentation/gpu: Add documentation about ring buffer
2025-08-24 23:29 [PATCH v2 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
` (3 preceding siblings ...)
2025-08-24 23:29 ` [PATCH v2 4/5] Documentation/gpu: Add more information about GC Rodrigo Siqueira
@ 2025-08-24 23:29 ` Rodrigo Siqueira
2025-08-25 15:58 ` Alex Deucher
4 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Siqueira @ 2025-08-24 23:29 UTC (permalink / raw)
To: Alex Deucher, Christian König, Timur Kristóf
Cc: amd-gfx, kernel-dev, Rodrigo Siqueira
AMDGPU heavily relies on ring buffers to manage its components; as a
result, it has an elaborate mechanism of operation with multiple details
around it. This commit introduces new documentation on ring buffers,
detailing their management and expanding the explanation of Enforce
isolation. Finally, this commit also adds the documentation available in
the amdgpu_ring.c file to it.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
---
.../gpu/amdgpu/enforce_isolation.svg | 707 +++++++
Documentation/gpu/amdgpu/gfx_pipeline_seq.svg | 413 +++++
Documentation/gpu/amdgpu/index.rst | 1 +
.../gpu/amdgpu/no_enforce_isolation.svg | 673 +++++++
Documentation/gpu/amdgpu/ring-buffer.rst | 94 +
Documentation/gpu/amdgpu/ring_buffers.svg | 1633 +++++++++++++++++
6 files changed, 3521 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg
diff --git a/Documentation/gpu/amdgpu/enforce_isolation.svg b/Documentation/gpu/amdgpu/enforce_isolation.svg
new file mode 100644
index 000000000000..b224615e1611
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+++ b/Documentation/gpu/amdgpu/enforce_isolation.svg
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diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
index bb2894b5edaf..1f0e8a38c625 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -8,6 +8,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
.. toctree::
driver-core
+ ring-buffer
amd-hardware-list-info
module-parameters
gc/index
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diff --git a/Documentation/gpu/amdgpu/ring-buffer.rst b/Documentation/gpu/amdgpu/ring-buffer.rst
new file mode 100644
index 000000000000..40c189c9dab4
--- /dev/null
+++ b/Documentation/gpu/amdgpu/ring-buffer.rst
@@ -0,0 +1,94 @@
+=============
+ Ring Buffer
+=============
+
+To handle communication between user space and kernel space, amdgpu adopts a
+strategy based on a ring buffer, which is used by GFX, Compute, SDMA, UVD, VCE,
+VCN, VPE, KIQ, MES, UMSCH, and CPER. See the figure below that illustrates how
+this communication works:
+
+.. kernel-figure:: ring_buffers.svg
+
+Ring buffers in the amdgpu work as a producer-consumer problem, where userspace
+acts as the producer, constantly filling the ring buffer with GPU commands to
+be executed. Meanwhile, the GPU retrieves the information from the ring, parses
+it, and distributes the specific set of instructions between the different
+amdgpu blocks. Notice from the diagram that the ring has a Read Pointer (rptr)
+that indicates where the GPU is currently reading, and there is a Write Pointer
+(wptr) that indicates where the host has written the message. Note that every
+time something is written to the ring, the wptr is incremented. Meanwhile, the
+GPU constantly updates the rptr pointer, chasing the wptr until both pointers
+are equal. The user space or the driver can utilize the rptr pointer to roughly
+estimate how many instructions are still pending completion (keep in mind that
+rptr might not be precise).
+
+Usually, ring buffers in the driver have a limited size (search for occurrences
+of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is
+that CP (Command Processor) is capable of following addresses inserted into the
+ring; this is illustrated in the image by the reference to the IB (Indirect
+Buffer). The IB gives userspace the possibility to have an area in memory that
+CP can read and feed the hardware with extra instructions.
+
+Enforce Isolation
+=================
+
+Before examining the Enforce Isolation mechanism in the ring buffer context, it
+is important to discuss two concepts: where the ring buffer is located and how
+instructions from the ring buffer are processed in the graphics pipeline.
+
+All ASICs pre-GFX11 use what is called a kernel queue, which means the ring is
+allocated in kernel space and has some restrictions, such as not being able to
+map and unmap queues after initialization. GFX12 and newer support kernel
+queues, but also provide a new mechanism named user queues, where the queue is
+moved to the user space and can be mapped and unmapped. In practical terms, the
+kernel queue approach inserts all GPU commands created by userspace into the
+same set of rings, albeit in a mixed manner. See the picture below illustrating
+this scenario:
+
+.. kernel-figure:: no_enforce_isolation.svg
+
+Note from the diagram that there is no guarantee of order or a clear separation
+between instructions, which is not a problem most of the time, and this is also
+good for performance. In terms of executing those instructions in the GFX, it
+must follow a pipeline that usually follows the following sequence: Shader
+Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan
+Converter (SC), Primitive Assembler (PA), and cache manipulation (this may
+change between ASICs). Another common way to describe the pipeline is to use
+Pixel Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader
+stages. The diagram below illustrates the sequence described in the paragraph.
+
+.. kernel-figure:: gfx_pipeline_seq.svg
+
+The use of the kernel queue is the default behaviour in amdgpu pre-GFX11 and in
+many cases in newer ASICs. Although this solution is considered stable and
+performs well, it also creates some intricate issues when something goes wrong.
+The problem with this solution is that pinpointing which job caused an issue
+can be challenging in some situations, which can complicate the debugging in
+circumstances where the GPU recovery was triggered. For instance, if Job A
+causes a hang issue, Job B's instruction might already be executing, and we
+could incorrectly identify Job B as the problematic one. To mitigate this
+problem, it was introduced the concept of Enforce Isolation that can be seen in
+the below picture:
+
+.. kernel-figure:: enforce_isolation.svg
+
+As shown in the diagram, enforcing isolation introduces a level of ordering
+between submissions, since the access to GFX/Compute is serialized. Notice that
+this approach has a minimal performance impact, as it only allows one job to
+submit commands at a time. However, this is not a notable problem, and the
+benefit of better pinpointing the job that caused a problem outweighs the
+performance impact. Although enforcing isolation improves the situation, it
+does not fully resolve the issue of pinpointing bad jobs, as we can still
+encounter scenarios where Job A hangs while Job B is running, leading to the
+wrong blame of Job B. To avoid this issue, an additional element is introduced
+to enforce isolation, as represented by the circles in the diagram. Every
+circle is a wait for cache flushing, which ensures that when the next job
+starts, it starts in a clean state, and if some issues happen, we can point to
+the bad process more precisely.
+
+Ring Operations
+===============
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+ :internal:
+
diff --git a/Documentation/gpu/amdgpu/ring_buffers.svg b/Documentation/gpu/amdgpu/ring_buffers.svg
new file mode 100644
index 000000000000..7a6fcb19e151
--- /dev/null
+++ b/Documentation/gpu/amdgpu/ring_buffers.svg
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2.47.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH v2 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring
2025-08-24 23:29 ` [PATCH v2 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
@ 2025-08-25 15:19 ` Christian König
2025-08-25 16:04 ` Timur Kristóf
0 siblings, 1 reply; 19+ messages in thread
From: Christian König @ 2025-08-25 15:19 UTC (permalink / raw)
To: Rodrigo Siqueira, Alex Deucher, Timur Kristóf; +Cc: amd-gfx, kernel-dev
On 25.08.25 01:29, Rodrigo Siqueira wrote:
> Expand the kernel-doc about amdgpu_ring and add some tiny improvements.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 14 +++++++++++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++
> 2 files changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> index 6379bb25bf5c..80dd6f58a53b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> @@ -75,8 +75,15 @@ unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type)
> * @ring: amdgpu_ring structure holding ring information
> * @ndw: number of dwords to allocate in the ring buffer
> *
> - * Allocate @ndw dwords in the ring buffer (all asics).
> - * Returns 0 on success, error on failure.
> + * Allocate @ndw dwords in the ring buffer (it works in all ASICs). When
> + * inspecting the code, you may encounter places where this function is called
> + * amdgpu_ring_alloc(ring, X + Y + Z), where X, Y, and Z are integer numbers.
> + * This indicates the number of dword operations to be inserted into the ring
> + * per operation.
I think explaining that is overkill, but the remaining comments are valid.
With the change above removed that patch is Reviewed-by: Christian König <christian.koenig@amd.com>.
Regards,
Christian.
> + *
> + * Returns:
> + * 0 on success, otherwise -ENOMEM if it tries to allocate more than the
> + * maximum dword allowed for one submission.
> */
> int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
> {
> @@ -122,7 +129,8 @@ static void amdgpu_ring_alloc_reemit(struct amdgpu_ring *ring, unsigned int ndw)
> ring->funcs->begin_use(ring);
> }
>
> -/** amdgpu_ring_insert_nop - insert NOP packets
> +/**
> + * amdgpu_ring_insert_nop - insert NOP packets
> *
> * @ring: amdgpu_ring structure holding ring information
> * @count: the number of NOP packets to insert
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 7670f5d82b9e..d27dbb3c109f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
> #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
> #define AMDGPU_FENCE_FLAG_INT (1 << 1)
> #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
> +
> +/* Ensure the execution in case of preemption or reset */
> #define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
>
> #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-24 23:29 ` [PATCH v2 4/5] Documentation/gpu: Add more information about GC Rodrigo Siqueira
@ 2025-08-25 15:38 ` Alex Deucher
2025-08-25 16:19 ` Timur Kristóf
0 siblings, 1 reply; 19+ messages in thread
From: Alex Deucher @ 2025-08-25 15:38 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: Alex Deucher, Christian König, Timur Kristóf, amd-gfx,
kernel-dev
On Sun, Aug 24, 2025 at 7:43 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> This commit introduces a diagram and a set of information that details
> the different sets of schedulers available in the SE.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
> Documentation/gpu/amdgpu/gc/cu.svg | 437 ++++++++++++++++++++++++++
> Documentation/gpu/amdgpu/gc/index.rst | 32 +-
> 2 files changed, 463 insertions(+), 6 deletions(-)
> create mode 100644 Documentation/gpu/amdgpu/gc/cu.svg
>
> diff --git a/Documentation/gpu/amdgpu/gc/cu.svg b/Documentation/gpu/amdgpu/gc/cu.svg
> new file mode 100644
> index 000000000000..10bdb3e24b65
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/gc/cu.svg
> @@ -0,0 +1,437 @@
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> diff --git a/Documentation/gpu/amdgpu/gc/index.rst b/Documentation/gpu/amdgpu/gc/index.rst
> index ff6e9ef5cbee..19f2ba53ee49 100644
> --- a/Documentation/gpu/amdgpu/gc/index.rst
> +++ b/Documentation/gpu/amdgpu/gc/index.rst
> @@ -10,16 +10,36 @@ producer-consumer problem, where the CPU fills out a buffer with operations
> the buffer are called Command Packets, which can be summarized as a compressed
> way of transmitting command information to the graphics controller.
>
> +In the diagram below, you can see an overview of the GC, along with additional
> +information about the Shader Engine (SE).
> +
> +.. kernel-figure:: cu.svg
Do you have a link to the images?
> +
> +First of all, note that the GC can have multiple SEs, depending on the specific
> +GPU/APU, and each SE has multiple Compute Units (CU). From the diagram, you can
> +see that CUs have a block named Schedulers. The reason the name is in plural is
> +because this hardware block is a combination of different micro-schedules: CP,
> +CPF, CPC, and CPG.
CP is not really in the same category as CPF, CPC, CPG. CP is the
front end to the GC block and contains a number of micro controllers
which run firmware which software interacts with. CPF, CPG, and CPC
are just hardware implementation details.
> +
> The component that acts as the front end between the CPU and the GPU is called
> -the Command Processor (CP). This component is responsible for providing greater
> +CP (Command Processor). This component is responsible for providing greater
> flexibility to the GC since CP makes it possible to program various aspects of
> the GPU pipeline. CP also coordinates the communication between the CPU and GPU
> via a mechanism named **Ring Buffers**, where the CPU appends information to
> -the buffer while the GPU removes operations. It is relevant to highlight that a
> -CPU can add a pointer to the Ring Buffer that points to another region of
> -memory outside the Ring Buffer, and CP can handle it; this mechanism is called
> -**Indirect Buffer (IB)**. CP receives and parses the Command Streams (CS), and
> -writes the operations to the correct hardware blocks.
> +the buffer while the GPU removes operations. Finally, CP is also responsible
> +for handling Indirect Buffers (IB).
> +
> +After CP completes the first set of processing, which includes separate command
> +packets specific to GFX and Compute, other blocks step in. To handle commands
> +for the compute block, CPC (Command Processor Command) takes over, and for
> +handling Graphics operations, the CPG (Command Processor Graphics) takes
> +action. Another essential block to ensure the optimal utilization of CPC and
> +CPG is the CPF (Command Processor Fetcher), which helps these blocks to be
> +constantly fed. Note that CPG contains the PFP (Pre-Fetch Parser), ME
> +(MicroEngine), and CE (Constant Engine) in the case of chips that support it.
> +CPC contains MEC (MicroEngine Compute), and CPF is another hardware block that
> +provides services to CPG and CPC.
I'm not sure how much value this provides to the average developer.
These are sort of implementation details of the hardware. In general
the driver doesn't really interact with the individual hardware blocks
and they may not stay consistent over time.
Alex
> +
>
> Graphics (GFX) and Compute Microcontrollers
> -------------------------------------------
> --
> 2.47.2
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 5/5] Documentation/gpu: Add documentation about ring buffer
2025-08-24 23:29 ` [PATCH v2 5/5] Documentation/gpu: Add documentation about ring buffer Rodrigo Siqueira
@ 2025-08-25 15:58 ` Alex Deucher
2025-08-26 23:53 ` Rodrigo Siqueira
0 siblings, 1 reply; 19+ messages in thread
From: Alex Deucher @ 2025-08-25 15:58 UTC (permalink / raw)
To: Rodrigo Siqueira
Cc: Alex Deucher, Christian König, Timur Kristóf, amd-gfx,
kernel-dev
On Sun, Aug 24, 2025 at 7:58 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
>
> AMDGPU heavily relies on ring buffers to manage its components; as a
> result, it has an elaborate mechanism of operation with multiple details
> around it. This commit introduces new documentation on ring buffers,
> detailing their management and expanding the explanation of Enforce
> isolation. Finally, this commit also adds the documentation available in
> the amdgpu_ring.c file to it.
>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: Christian König <christian.koenig@amd.com>
> Cc: Timur Kristóf <timur.kristof@gmail.com>
> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> ---
> .../gpu/amdgpu/enforce_isolation.svg | 707 +++++++
> Documentation/gpu/amdgpu/gfx_pipeline_seq.svg | 413 +++++
> Documentation/gpu/amdgpu/index.rst | 1 +
> .../gpu/amdgpu/no_enforce_isolation.svg | 673 +++++++
> Documentation/gpu/amdgpu/ring-buffer.rst | 94 +
> Documentation/gpu/amdgpu/ring_buffers.svg | 1633 +++++++++++++++++
> 6 files changed, 3521 insertions(+)
> create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
> create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
> create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
> create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
> create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg
>
Do you have links to the images?
> diff --git a/Documentation/gpu/amdgpu/enforce_isolation.svg b/Documentation/gpu/amdgpu/enforce_isolation.svg
> new file mode 100644
> index 000000000000..b224615e1611
> --- /dev/null
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> diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
> index bb2894b5edaf..1f0e8a38c625 100644
> --- a/Documentation/gpu/amdgpu/index.rst
> +++ b/Documentation/gpu/amdgpu/index.rst
> @@ -8,6 +8,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
> .. toctree::
>
> driver-core
> + ring-buffer
> amd-hardware-list-info
> module-parameters
> gc/index
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> new file mode 100644
> index 000000000000..38735447b005
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> diff --git a/Documentation/gpu/amdgpu/ring-buffer.rst b/Documentation/gpu/amdgpu/ring-buffer.rst
> new file mode 100644
> index 000000000000..40c189c9dab4
> --- /dev/null
> +++ b/Documentation/gpu/amdgpu/ring-buffer.rst
> @@ -0,0 +1,94 @@
> +=============
> + Ring Buffer
> +=============
> +
> +To handle communication between user space and kernel space, amdgpu adopts a
> +strategy based on a ring buffer, which is used by GFX, Compute, SDMA, UVD, VCE,
> +VCN, VPE, KIQ, MES, UMSCH, and CPER. See the figure below that illustrates how
> +this communication works:
> +
> +.. kernel-figure:: ring_buffers.svg
> +
> +Ring buffers in the amdgpu work as a producer-consumer problem, where userspace
> +acts as the producer, constantly filling the ring buffer with GPU commands to
> +be executed. Meanwhile, the GPU retrieves the information from the ring, parses
> +it, and distributes the specific set of instructions between the different
> +amdgpu blocks. Notice from the diagram that the ring has a Read Pointer (rptr)
> +that indicates where the GPU is currently reading, and there is a Write Pointer
> +(wptr) that indicates where the host has written the message. Note that every
> +time something is written to the ring, the wptr is incremented. Meanwhile, the
> +GPU constantly updates the rptr pointer, chasing the wptr until both pointers
> +are equal. The user space or the driver can utilize the rptr pointer to roughly
User space or the driver
> +estimate how many instructions are still pending completion (keep in mind that
> +rptr might not be precise).
You might want to drop the comment in the paranthesis. If you read
back the actual
rptr register, it should be correct, but the driver generally uses a
rptr shadow in memory which the engine may only update periodically.
> +
> +Usually, ring buffers in the driver have a limited size (search for occurrences
> +of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is
> +that CP (Command Processor) is capable of following addresses inserted into the
> +ring; this is illustrated in the image by the reference to the IB (Indirect
> +Buffer). The IB gives userspace the possibility to have an area in memory that
> +CP can read and feed the hardware with extra instructions.
> +
> +Enforce Isolation
> +=================
> +
> +Before examining the Enforce Isolation mechanism in the ring buffer context, it
> +is important to discuss two concepts: where the ring buffer is located and how
> +instructions from the ring buffer are processed in the graphics pipeline.
> +
> +All ASICs pre-GFX11 use what is called a kernel queue, which means the ring is
gfx11 and 12 still use kernel queues, they just happen to also support
user queues.
> +allocated in kernel space and has some restrictions, such as not being able to
> +map and unmap queues after initialization. GFX12 and newer support kernel
Kernel queues can be mapped an unmapped, the scheduler just never preempts them.
> +queues, but also provide a new mechanism named user queues, where the queue is
> +moved to the user space and can be mapped and unmapped. In practical terms, the
> +kernel queue approach inserts all GPU commands created by userspace into the
> +same set of rings, albeit in a mixed manner. See the picture below illustrating
> +this scenario:
> +
> +.. kernel-figure:: no_enforce_isolation.svg
> +
> +Note from the diagram that there is no guarantee of order or a clear separation
> +between instructions, which is not a problem most of the time, and this is also
I haven't looked at the images yet, but the jobs are added
sequentially, it's just that because the GC engine is pipelined, you
can have multiple things overlapping.
> +good for performance. In terms of executing those instructions in the GFX, it
> +must follow a pipeline that usually follows the following sequence: Shader
> +Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan
> +Converter (SC), Primitive Assembler (PA), and cache manipulation (this may
> +change between ASICs). Another common way to describe the pipeline is to use
> +Pixel Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader
> +stages. The diagram below illustrates the sequence described in the paragraph.
I think the rest of this paragraph is unrelated to enforce isolation.
I think it should be moved somewhere else to describe the hardware
pipeline.
> +
> +.. kernel-figure:: gfx_pipeline_seq.svg
> +
> +The use of the kernel queue is the default behaviour in amdgpu pre-GFX11 and in
> +many cases in newer ASICs. Although this solution is considered stable and
> +performs well, it also creates some intricate issues when something goes wrong.
> +The problem with this solution is that pinpointing which job caused an issue
> +can be challenging in some situations, which can complicate the debugging in
> +circumstances where the GPU recovery was triggered. For instance, if Job A
> +causes a hang issue, Job B's instruction might already be executing, and we
> +could incorrectly identify Job B as the problematic one. To mitigate this
> +problem, it was introduced the concept of Enforce Isolation that can be seen in
> +the below picture:
> +
> +.. kernel-figure:: enforce_isolation.svg
> +
> +As shown in the diagram, enforcing isolation introduces a level of ordering
> +between submissions, since the access to GFX/Compute is serialized. Notice that
> +this approach has a minimal performance impact, as it only allows one job to
> +submit commands at a time. However, this is not a notable problem, and the
> +benefit of better pinpointing the job that caused a problem outweighs the
> +performance impact. Although enforcing isolation improves the situation, it
> +does not fully resolve the issue of pinpointing bad jobs, as we can still
> +encounter scenarios where Job A hangs while Job B is running, leading to the
> +wrong blame of Job B. To avoid this issue, an additional element is introduced
> +to enforce isolation, as represented by the circles in the diagram. Every
> +circle is a wait for cache flushing, which ensures that when the next job
> +starts, it starts in a clean state, and if some issues happen, we can point to
> +the bad process more precisely.
I haven't seen the diagram yet, but this doesn't sound completely
correct. The driver inserts a fence wait between jobs in each ring to
make sure there is no overlapping work in the ring itself. However,
that is independent of enforce isolation. If you enable enforce
isolation, all jobs going to all GC queues are serialized.
Alex
> +
> +Ring Operations
> +===============
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> + :internal:
> +
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>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring
2025-08-25 15:19 ` Christian König
@ 2025-08-25 16:04 ` Timur Kristóf
0 siblings, 0 replies; 19+ messages in thread
From: Timur Kristóf @ 2025-08-25 16:04 UTC (permalink / raw)
To: Christian König, Rodrigo Siqueira, Alex Deucher; +Cc: amd-gfx, kernel-dev
Hi,
On Mon, 2025-08-25 at 17:19 +0200, Christian König wrote:
> On 25.08.25 01:29, Rodrigo Siqueira wrote:
> > Expand the kernel-doc about amdgpu_ring and add some tiny
> > improvements.
> >
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Christian König <christian.koenig@amd.com>
> > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 14 +++++++++++---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++
> > 2 files changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > index 6379bb25bf5c..80dd6f58a53b 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > @@ -75,8 +75,15 @@ unsigned int amdgpu_ring_max_ibs(enum
> > amdgpu_ring_type type)
> > * @ring: amdgpu_ring structure holding ring information
> > * @ndw: number of dwords to allocate in the ring buffer
> > *
>
> > - * Allocate @ndw dwords in the ring buffer (all asics).
> > - * Returns 0 on success, error on failure.
> > + * Allocate @ndw dwords in the ring buffer (it works in all
> > ASICs). When
> > + * inspecting the code, you may encounter places where this
> > function is called
> > + * amdgpu_ring_alloc(ring, X + Y + Z), where X, Y, and Z are
> > integer numbers.
> > + * This indicates the number of dword operations to be inserted
> > into the ring
> > + * per operation.
>
> I think explaining that is overkill, but the remaining comments are
> valid.
>
> With the change above removed that patch is Reviewed-by: Christian
> König <christian.koenig@amd.com>.
>
> Regards,
> Christian.
I respectfully disagree with that.
This stuff may be obvious to you, having worked on it for many years.
But it was super confusing to me when I first looked at it, so I'm glad
to see Siquiera added it here. It may help the next newcomer.
As a side note, in many places it's not fully clear when something is
in bytes vs. dwords so it's also good to emphasize that these represent
dwords of packets.
>
> > + *
> > + * Returns:
> > + * 0 on success, otherwise -ENOMEM if it tries to allocate more
> > than the
> > + * maximum dword allowed for one submission.
> > */
> > int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned int ndw)
> > {
> > @@ -122,7 +129,8 @@ static void amdgpu_ring_alloc_reemit(struct
> > amdgpu_ring *ring, unsigned int ndw)
> > ring->funcs->begin_use(ring);
> > }
> >
> > -/** amdgpu_ring_insert_nop - insert NOP packets
> > +/**
> > + * amdgpu_ring_insert_nop - insert NOP packets
> > *
> > * @ring: amdgpu_ring structure holding ring information
> > * @count: the number of NOP packets to insert
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > index 7670f5d82b9e..d27dbb3c109f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > @@ -62,6 +62,8 @@ enum amdgpu_ring_priority_level {
> > #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
> > #define AMDGPU_FENCE_FLAG_INT (1 << 1)
> > #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
> > +
> > +/* Ensure the execution in case of preemption or reset */
> > #define AMDGPU_FENCE_FLAG_EXEC (1 << 3)
> >
> > #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring,
> > sched)
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-25 15:38 ` Alex Deucher
@ 2025-08-25 16:19 ` Timur Kristóf
2025-08-25 16:31 ` Alex Deucher
0 siblings, 1 reply; 19+ messages in thread
From: Timur Kristóf @ 2025-08-25 16:19 UTC (permalink / raw)
To: Alex Deucher, Rodrigo Siqueira
Cc: Alex Deucher, Christian König, amd-gfx, kernel-dev
On Mon, 2025-08-25 at 11:38 -0400, Alex Deucher wrote:
> On Sun, Aug 24, 2025 at 7:43 PM Rodrigo Siqueira
> <siqueira@igalia.com> wrote:
>
>
> > +
> > +First of all, note that the GC can have multiple SEs, depending on
> > the specific
> > +GPU/APU, and each SE has multiple Compute Units (CU). From the
> > diagram, you can
> > +see that CUs have a block named Schedulers. The reason the name is
> > in plural is
> > +because this hardware block is a combination of different micro-
> > schedules: CP,
> > +CPF, CPC, and CPG.
>
> CP is not really in the same category as CPF, CPC, CPG. CP is the
> front end to the GC block and contains a number of micro controllers
> which run firmware which software interacts with. CPF, CPG, and CPC
> are just hardware implementation details.
Can you please suggest an edit that explains these better?
I'm sorry to say, I thought I understood it but after reading your
reply now I feel I don't.
>
> > +
> > The component that acts as the front end between the CPU and the
> > GPU is called
> > -the Command Processor (CP). This component is responsible for
> > providing greater
> > +CP (Command Processor). This component is responsible for
> > providing greater
> > flexibility to the GC since CP makes it possible to program
> > various aspects of
> > the GPU pipeline. CP also coordinates the communication between
> > the CPU and GPU
> > via a mechanism named **Ring Buffers**, where the CPU appends
> > information to
> > -the buffer while the GPU removes operations. It is relevant to
> > highlight that a
> > -CPU can add a pointer to the Ring Buffer that points to another
> > region of
> > -memory outside the Ring Buffer, and CP can handle it; this
> > mechanism is called
> > -**Indirect Buffer (IB)**. CP receives and parses the Command
> > Streams (CS), and
> > -writes the operations to the correct hardware blocks.
> > +the buffer while the GPU removes operations. Finally, CP is also
> > responsible
> > +for handling Indirect Buffers (IB).
> > +
> > +After CP completes the first set of processing, which includes
> > separate command
> > +packets specific to GFX and Compute, other blocks step in. To
> > handle commands
> > +for the compute block, CPC (Command Processor Command) takes over,
> > and for
> > +handling Graphics operations, the CPG (Command Processor Graphics)
> > takes
> > +action. Another essential block to ensure the optimal utilization
> > of CPC and
> > +CPG is the CPF (Command Processor Fetcher), which helps these
> > blocks to be
> > +constantly fed. Note that CPG contains the PFP (Pre-Fetch Parser),
> > ME
> > +(MicroEngine), and CE (Constant Engine) in the case of chips that
> > support it.
> > +CPC contains MEC (MicroEngine Compute), and CPF is another
> > hardware block that
> > +provides services to CPG and CPC.
>
> I'm not sure how much value this provides to the average developer.
> These are sort of implementation details of the hardware. In general
> the driver doesn't really interact with the individual hardware
> blocks
> and they may not stay consistent over time.
>
> Alex
Not sure what you mean by "the average developer", but I think this is
very useful knowledge to anyone who wants to contribute to amdgpu,
specifically to the parts that have anything to do with GFX or compute.
If you're worried that it may not stay consistent over time, I think
the glossary entries could be edited to mention which GPU generation(s)
they apply to.
As-is the code is full of 3-letter abbreviations that are never
expanded or explained anywhere, which represent various hardware units
(or microcontrollers, or blocks, or whatever they may be). Without
knowing what these are and how they interact, it's difficult to
understand what the code is doing any why, or even why some parts are
necessary.
To make matters worse, the latest public documentation that tries to
explain any of this is from 2012. So I think it's a good idea to
collect all of this information so that newcomers to the kernel driver
such as myself have a chance.
Thanks & best regards,
Timur
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-25 16:19 ` Timur Kristóf
@ 2025-08-25 16:31 ` Alex Deucher
2025-08-25 16:39 ` Timur Kristóf
0 siblings, 1 reply; 19+ messages in thread
From: Alex Deucher @ 2025-08-25 16:31 UTC (permalink / raw)
To: Timur Kristóf
Cc: Rodrigo Siqueira, Alex Deucher, Christian König, amd-gfx,
kernel-dev
On Mon, Aug 25, 2025 at 12:19 PM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On Mon, 2025-08-25 at 11:38 -0400, Alex Deucher wrote:
> > On Sun, Aug 24, 2025 at 7:43 PM Rodrigo Siqueira
> > <siqueira@igalia.com> wrote:
> >
> >
> > > +
> > > +First of all, note that the GC can have multiple SEs, depending on
> > > the specific
> > > +GPU/APU, and each SE has multiple Compute Units (CU). From the
> > > diagram, you can
> > > +see that CUs have a block named Schedulers. The reason the name is
> > > in plural is
> > > +because this hardware block is a combination of different micro-
> > > schedules: CP,
> > > +CPF, CPC, and CPG.
> >
> > CP is not really in the same category as CPF, CPC, CPG. CP is the
> > front end to the GC block and contains a number of micro controllers
> > which run firmware which software interacts with. CPF, CPG, and CPC
> > are just hardware implementation details.
>
> Can you please suggest an edit that explains these better?
>
> I'm sorry to say, I thought I understood it but after reading your
> reply now I feel I don't.
I would say something like:
The CP (Command Processor) is the front end to the GC hardware. It
provides microcontrollers which manage command queues which are used
to feed jobs to the GFX and compute hardware.
>
> >
> > > +
> > > The component that acts as the front end between the CPU and the
> > > GPU is called
> > > -the Command Processor (CP). This component is responsible for
> > > providing greater
> > > +CP (Command Processor). This component is responsible for
> > > providing greater
> > > flexibility to the GC since CP makes it possible to program
> > > various aspects of
> > > the GPU pipeline. CP also coordinates the communication between
> > > the CPU and GPU
> > > via a mechanism named **Ring Buffers**, where the CPU appends
> > > information to
> > > -the buffer while the GPU removes operations. It is relevant to
> > > highlight that a
> > > -CPU can add a pointer to the Ring Buffer that points to another
> > > region of
> > > -memory outside the Ring Buffer, and CP can handle it; this
> > > mechanism is called
> > > -**Indirect Buffer (IB)**. CP receives and parses the Command
> > > Streams (CS), and
> > > -writes the operations to the correct hardware blocks.
> > > +the buffer while the GPU removes operations. Finally, CP is also
> > > responsible
> > > +for handling Indirect Buffers (IB).
> > > +
> > > +After CP completes the first set of processing, which includes
> > > separate command
> > > +packets specific to GFX and Compute, other blocks step in. To
> > > handle commands
> > > +for the compute block, CPC (Command Processor Command) takes over,
> > > and for
> > > +handling Graphics operations, the CPG (Command Processor Graphics)
> > > takes
> > > +action. Another essential block to ensure the optimal utilization
> > > of CPC and
> > > +CPG is the CPF (Command Processor Fetcher), which helps these
> > > blocks to be
> > > +constantly fed. Note that CPG contains the PFP (Pre-Fetch Parser),
> > > ME
> > > +(MicroEngine), and CE (Constant Engine) in the case of chips that
> > > support it.
> > > +CPC contains MEC (MicroEngine Compute), and CPF is another
> > > hardware block that
> > > +provides services to CPG and CPC.
> >
> > I'm not sure how much value this provides to the average developer.
> > These are sort of implementation details of the hardware. In general
> > the driver doesn't really interact with the individual hardware
> > blocks
> > and they may not stay consistent over time.
> >
> > Alex
>
> Not sure what you mean by "the average developer", but I think this is
> very useful knowledge to anyone who wants to contribute to amdgpu,
> specifically to the parts that have anything to do with GFX or compute.
>
> If you're worried that it may not stay consistent over time, I think
> the glossary entries could be edited to mention which GPU generation(s)
> they apply to.
>
> As-is the code is full of 3-letter abbreviations that are never
> expanded or explained anywhere, which represent various hardware units
> (or microcontrollers, or blocks, or whatever they may be). Without
> knowing what these are and how they interact, it's difficult to
> understand what the code is doing any why, or even why some parts are
> necessary.
>
> To make matters worse, the latest public documentation that tries to
> explain any of this is from 2012. So I think it's a good idea to
> collect all of this information so that newcomers to the kernel driver
> such as myself have a chance.
The driver/developers don't interact with CPF, CPC, CPG directly.
They just happen to be arbitrary sub-blocks of the CP. I'm concerned
that adding a lot of stuff about them will just lead to confusion.
Documenting the micro controllers which run the firmwares makes sense
as those are how the driver interacts with the CP block.
CE/PFP/ME - Microcontrollers which run the firmware that provides the
graphics command queues that the driver interacts with.
MEC - Microcontrollers which run the firmware that provides the
compute command queues that the driver interacts with.
MES - Microcontrollers which run the firmware that provides the
command queues that the driver uses to manage graphics and compute
command queues.
Alex
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-25 16:31 ` Alex Deucher
@ 2025-08-25 16:39 ` Timur Kristóf
2025-08-25 17:06 ` Alex Deucher
0 siblings, 1 reply; 19+ messages in thread
From: Timur Kristóf @ 2025-08-25 16:39 UTC (permalink / raw)
To: Alex Deucher
Cc: Rodrigo Siqueira, Alex Deucher, Christian König, amd-gfx,
kernel-dev
On Mon, 2025-08-25 at 12:31 -0400, Alex Deucher wrote:
> On Mon, Aug 25, 2025 at 12:19 PM Timur Kristóf
> <timur.kristof@gmail.com> wrote:
> >
> > On Mon, 2025-08-25 at 11:38 -0400, Alex Deucher wrote:
> > > On Sun, Aug 24, 2025 at 7:43 PM Rodrigo Siqueira
> > > <siqueira@igalia.com> wrote:
> > >
> > >
> > > > +
> > > > +First of all, note that the GC can have multiple SEs,
> > > > depending on
> > > > the specific
> > > > +GPU/APU, and each SE has multiple Compute Units (CU). From the
> > > > diagram, you can
> > > > +see that CUs have a block named Schedulers. The reason the
> > > > name is
> > > > in plural is
> > > > +because this hardware block is a combination of different
> > > > micro-
> > > > schedules: CP,
> > > > +CPF, CPC, and CPG.
> > >
> > > CP is not really in the same category as CPF, CPC, CPG. CP is
> > > the
> > > front end to the GC block and contains a number of micro
> > > controllers
> > > which run firmware which software interacts with. CPF, CPG, and
> > > CPC
> > > are just hardware implementation details.
> >
> > Can you please suggest an edit that explains these better?
> >
> > I'm sorry to say, I thought I understood it but after reading your
> > reply now I feel I don't.
>
> I would say something like:
>
> The CP (Command Processor) is the front end to the GC hardware. It
> provides microcontrollers which manage command queues which are used
> to feed jobs to the GFX and compute hardware.
Sounds good. What do you think, Siquiera?
>
> >
> > >
> > > > +
> > > > The component that acts as the front end between the CPU and
> > > > the
> > > > GPU is called
> > > > -the Command Processor (CP). This component is responsible for
> > > > providing greater
> > > > +CP (Command Processor). This component is responsible for
> > > > providing greater
> > > > flexibility to the GC since CP makes it possible to program
> > > > various aspects of
> > > > the GPU pipeline. CP also coordinates the communication
> > > > between
> > > > the CPU and GPU
> > > > via a mechanism named **Ring Buffers**, where the CPU appends
> > > > information to
> > > > -the buffer while the GPU removes operations. It is relevant to
> > > > highlight that a
> > > > -CPU can add a pointer to the Ring Buffer that points to
> > > > another
> > > > region of
> > > > -memory outside the Ring Buffer, and CP can handle it; this
> > > > mechanism is called
> > > > -**Indirect Buffer (IB)**. CP receives and parses the Command
> > > > Streams (CS), and
> > > > -writes the operations to the correct hardware blocks.
> > > > +the buffer while the GPU removes operations. Finally, CP is
> > > > also
> > > > responsible
> > > > +for handling Indirect Buffers (IB).
> > > > +
> > > > +After CP completes the first set of processing, which includes
> > > > separate command
> > > > +packets specific to GFX and Compute, other blocks step in. To
> > > > handle commands
> > > > +for the compute block, CPC (Command Processor Command) takes
> > > > over,
> > > > and for
> > > > +handling Graphics operations, the CPG (Command Processor
> > > > Graphics)
> > > > takes
> > > > +action. Another essential block to ensure the optimal
> > > > utilization
> > > > of CPC and
> > > > +CPG is the CPF (Command Processor Fetcher), which helps these
> > > > blocks to be
> > > > +constantly fed. Note that CPG contains the PFP (Pre-Fetch
> > > > Parser),
> > > > ME
> > > > +(MicroEngine), and CE (Constant Engine) in the case of chips
> > > > that
> > > > support it.
> > > > +CPC contains MEC (MicroEngine Compute), and CPF is another
> > > > hardware block that
> > > > +provides services to CPG and CPC.
> > >
> > > I'm not sure how much value this provides to the average
> > > developer.
> > > These are sort of implementation details of the hardware. In
> > > general
> > > the driver doesn't really interact with the individual hardware
> > > blocks
> > > and they may not stay consistent over time.
> > >
> > > Alex
> >
> > Not sure what you mean by "the average developer", but I think this
> > is
> > very useful knowledge to anyone who wants to contribute to amdgpu,
> > specifically to the parts that have anything to do with GFX or
> > compute.
> >
> > If you're worried that it may not stay consistent over time, I
> > think
> > the glossary entries could be edited to mention which GPU
> > generation(s)
> > they apply to.
> >
> > As-is the code is full of 3-letter abbreviations that are never
> > expanded or explained anywhere, which represent various hardware
> > units
> > (or microcontrollers, or blocks, or whatever they may be). Without
> > knowing what these are and how they interact, it's difficult to
> > understand what the code is doing any why, or even why some parts
> > are
> > necessary.
> >
> > To make matters worse, the latest public documentation that tries
> > to
> > explain any of this is from 2012. So I think it's a good idea to
> > collect all of this information so that newcomers to the kernel
> > driver
> > such as myself have a chance.
>
> The driver/developers don't interact with CPF, CPC, CPG directly.
> They just happen to be arbitrary sub-blocks of the CP. I'm concerned
> that adding a lot of stuff about them will just lead to confusion.
I think they are worth a sentence or two each in the glossary.
When trying to diagnose problems (eg. GPU hangs), we often need to look
at various HW registers (eg. GRBM_STATUS), which refer to the above
sub-blocks. It is then hard to see what is going on without knowing
what these are. In turn, that makes it hard to come up with an
understanding that can explain what is happening on the HW.
>
> Documenting the micro controllers which run the firmwares makes sense
> as those are how the driver interacts with the CP block.
>
> CE/PFP/ME - Microcontrollers which run the firmware that provides the
> graphics command queues that the driver interacts with.
> MEC - Microcontrollers which run the firmware that provides the
> compute command queues that the driver interacts with.
> MES - Microcontrollers which run the firmware that provides the
> command queues that the driver uses to manage graphics and compute
> command queues.
I agree and I think most (all?) of these are already in the glossary.
If not, they should be definitely added.
Thanks & best regards,
Timur
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-25 16:39 ` Timur Kristóf
@ 2025-08-25 17:06 ` Alex Deucher
2025-08-25 21:18 ` Timur Kristóf
0 siblings, 1 reply; 19+ messages in thread
From: Alex Deucher @ 2025-08-25 17:06 UTC (permalink / raw)
To: Timur Kristóf
Cc: Rodrigo Siqueira, Alex Deucher, Christian König, amd-gfx,
kernel-dev
On Mon, Aug 25, 2025 at 12:39 PM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On Mon, 2025-08-25 at 12:31 -0400, Alex Deucher wrote:
> > On Mon, Aug 25, 2025 at 12:19 PM Timur Kristóf
> > <timur.kristof@gmail.com> wrote:
> > >
> > > On Mon, 2025-08-25 at 11:38 -0400, Alex Deucher wrote:
> > > > On Sun, Aug 24, 2025 at 7:43 PM Rodrigo Siqueira
> > > > <siqueira@igalia.com> wrote:
> > > >
> > > >
> > > > > +
> > > > > +First of all, note that the GC can have multiple SEs,
> > > > > depending on
> > > > > the specific
> > > > > +GPU/APU, and each SE has multiple Compute Units (CU). From the
> > > > > diagram, you can
> > > > > +see that CUs have a block named Schedulers. The reason the
> > > > > name is
> > > > > in plural is
> > > > > +because this hardware block is a combination of different
> > > > > micro-
> > > > > schedules: CP,
> > > > > +CPF, CPC, and CPG.
> > > >
> > > > CP is not really in the same category as CPF, CPC, CPG. CP is
> > > > the
> > > > front end to the GC block and contains a number of micro
> > > > controllers
> > > > which run firmware which software interacts with. CPF, CPG, and
> > > > CPC
> > > > are just hardware implementation details.
> > >
> > > Can you please suggest an edit that explains these better?
> > >
> > > I'm sorry to say, I thought I understood it but after reading your
> > > reply now I feel I don't.
> >
> > I would say something like:
> >
> > The CP (Command Processor) is the front end to the GC hardware. It
> > provides microcontrollers which manage command queues which are used
> > to feed jobs to the GFX and compute hardware.
>
> Sounds good. What do you think, Siquiera?
>
> >
> > >
> > > >
> > > > > +
> > > > > The component that acts as the front end between the CPU and
> > > > > the
> > > > > GPU is called
> > > > > -the Command Processor (CP). This component is responsible for
> > > > > providing greater
> > > > > +CP (Command Processor). This component is responsible for
> > > > > providing greater
> > > > > flexibility to the GC since CP makes it possible to program
> > > > > various aspects of
> > > > > the GPU pipeline. CP also coordinates the communication
> > > > > between
> > > > > the CPU and GPU
> > > > > via a mechanism named **Ring Buffers**, where the CPU appends
> > > > > information to
> > > > > -the buffer while the GPU removes operations. It is relevant to
> > > > > highlight that a
> > > > > -CPU can add a pointer to the Ring Buffer that points to
> > > > > another
> > > > > region of
> > > > > -memory outside the Ring Buffer, and CP can handle it; this
> > > > > mechanism is called
> > > > > -**Indirect Buffer (IB)**. CP receives and parses the Command
> > > > > Streams (CS), and
> > > > > -writes the operations to the correct hardware blocks.
> > > > > +the buffer while the GPU removes operations. Finally, CP is
> > > > > also
> > > > > responsible
> > > > > +for handling Indirect Buffers (IB).
> > > > > +
> > > > > +After CP completes the first set of processing, which includes
> > > > > separate command
> > > > > +packets specific to GFX and Compute, other blocks step in. To
> > > > > handle commands
> > > > > +for the compute block, CPC (Command Processor Command) takes
> > > > > over,
> > > > > and for
> > > > > +handling Graphics operations, the CPG (Command Processor
> > > > > Graphics)
> > > > > takes
> > > > > +action. Another essential block to ensure the optimal
> > > > > utilization
> > > > > of CPC and
> > > > > +CPG is the CPF (Command Processor Fetcher), which helps these
> > > > > blocks to be
> > > > > +constantly fed. Note that CPG contains the PFP (Pre-Fetch
> > > > > Parser),
> > > > > ME
> > > > > +(MicroEngine), and CE (Constant Engine) in the case of chips
> > > > > that
> > > > > support it.
> > > > > +CPC contains MEC (MicroEngine Compute), and CPF is another
> > > > > hardware block that
> > > > > +provides services to CPG and CPC.
> > > >
> > > > I'm not sure how much value this provides to the average
> > > > developer.
> > > > These are sort of implementation details of the hardware. In
> > > > general
> > > > the driver doesn't really interact with the individual hardware
> > > > blocks
> > > > and they may not stay consistent over time.
> > > >
> > > > Alex
> > >
> > > Not sure what you mean by "the average developer", but I think this
> > > is
> > > very useful knowledge to anyone who wants to contribute to amdgpu,
> > > specifically to the parts that have anything to do with GFX or
> > > compute.
> > >
> > > If you're worried that it may not stay consistent over time, I
> > > think
> > > the glossary entries could be edited to mention which GPU
> > > generation(s)
> > > they apply to.
> > >
> > > As-is the code is full of 3-letter abbreviations that are never
> > > expanded or explained anywhere, which represent various hardware
> > > units
> > > (or microcontrollers, or blocks, or whatever they may be). Without
> > > knowing what these are and how they interact, it's difficult to
> > > understand what the code is doing any why, or even why some parts
> > > are
> > > necessary.
> > >
> > > To make matters worse, the latest public documentation that tries
> > > to
> > > explain any of this is from 2012. So I think it's a good idea to
> > > collect all of this information so that newcomers to the kernel
> > > driver
> > > such as myself have a chance.
> >
> > The driver/developers don't interact with CPF, CPC, CPG directly.
> > They just happen to be arbitrary sub-blocks of the CP. I'm concerned
> > that adding a lot of stuff about them will just lead to confusion.
>
> I think they are worth a sentence or two each in the glossary.
>
> When trying to diagnose problems (eg. GPU hangs), we often need to look
> at various HW registers (eg. GRBM_STATUS), which refer to the above
> sub-blocks. It is then hard to see what is going on without knowing
> what these are. In turn, that makes it hard to come up with an
> understanding that can explain what is happening on the HW.
>
I think that's fine. I just don't want to put too much emphasis on
them since they are more of an implementation detail within the CP.
They aren't quite the same as the other blocks that make up the GC
pipeline from a driver or debugging standpoint.
> >
> > Documenting the micro controllers which run the firmwares makes sense
> > as those are how the driver interacts with the CP block.
> >
> > CE/PFP/ME - Microcontrollers which run the firmware that provides the
> > graphics command queues that the driver interacts with.
> > MEC - Microcontrollers which run the firmware that provides the
> > compute command queues that the driver interacts with.
> > MES - Microcontrollers which run the firmware that provides the
> > command queues that the driver uses to manage graphics and compute
> > command queues.
>
> I agree and I think most (all?) of these are already in the glossary.
> If not, they should be definitely added.
>
> Thanks & best regards,
> Timur
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-25 17:06 ` Alex Deucher
@ 2025-08-25 21:18 ` Timur Kristóf
2025-08-26 13:21 ` Alex Deucher
0 siblings, 1 reply; 19+ messages in thread
From: Timur Kristóf @ 2025-08-25 21:18 UTC (permalink / raw)
To: Alex Deucher
Cc: Rodrigo Siqueira, Alex Deucher, Christian König, amd-gfx,
kernel-dev
On Mon, 2025-08-25 at 13:06 -0400, Alex Deucher wrote:
> On Mon, Aug 25, 2025 at 12:39 PM Timur Kristóf
> <timur.kristof@gmail.com> wrote:
> >
> > On Mon, 2025-08-25 at 12:31 -0400, Alex Deucher wrote:
> > > On Mon, Aug 25, 2025 at 12:19 PM Timur Kristóf
> > > <timur.kristof@gmail.com> wrote:
> > > >
> > > > On Mon, 2025-08-25 at 11:38 -0400, Alex Deucher wrote:
> > > > > On Sun, Aug 24, 2025 at 7:43 PM Rodrigo Siqueira
> > > > > <siqueira@igalia.com> wrote:
> > > > >
> > > > >
> > > > > > +
> > > > > > +First of all, note that the GC can have multiple SEs,
> > > > > > depending on
> > > > > > the specific
> > > > > > +GPU/APU, and each SE has multiple Compute Units (CU). From
> > > > > > the
> > > > > > diagram, you can
> > > > > > +see that CUs have a block named Schedulers. The reason the
> > > > > > name is
> > > > > > in plural is
> > > > > > +because this hardware block is a combination of different
> > > > > > micro-
> > > > > > schedules: CP,
> > > > > > +CPF, CPC, and CPG.
> > > > >
> > > > > CP is not really in the same category as CPF, CPC, CPG. CP
> > > > > is
> > > > > the
> > > > > front end to the GC block and contains a number of micro
> > > > > controllers
> > > > > which run firmware which software interacts with. CPF, CPG,
> > > > > and
> > > > > CPC
> > > > > are just hardware implementation details.
> > > >
> > > > Can you please suggest an edit that explains these better?
> > > >
> > > > I'm sorry to say, I thought I understood it but after reading
> > > > your
> > > > reply now I feel I don't.
> > >
> > > I would say something like:
> > >
> > > The CP (Command Processor) is the front end to the GC hardware.
> > > It
> > > provides microcontrollers which manage command queues which are
> > > used
> > > to feed jobs to the GFX and compute hardware.
> >
> > Sounds good. What do you think, Siquiera?
> >
> > >
> > > >
> > > > >
> > > > > > +
> > > > > > The component that acts as the front end between the CPU
> > > > > > and
> > > > > > the
> > > > > > GPU is called
> > > > > > -the Command Processor (CP). This component is responsible
> > > > > > for
> > > > > > providing greater
> > > > > > +CP (Command Processor). This component is responsible for
> > > > > > providing greater
> > > > > > flexibility to the GC since CP makes it possible to
> > > > > > program
> > > > > > various aspects of
> > > > > > the GPU pipeline. CP also coordinates the communication
> > > > > > between
> > > > > > the CPU and GPU
> > > > > > via a mechanism named **Ring Buffers**, where the CPU
> > > > > > appends
> > > > > > information to
> > > > > > -the buffer while the GPU removes operations. It is
> > > > > > relevant to
> > > > > > highlight that a
> > > > > > -CPU can add a pointer to the Ring Buffer that points to
> > > > > > another
> > > > > > region of
> > > > > > -memory outside the Ring Buffer, and CP can handle it; this
> > > > > > mechanism is called
> > > > > > -**Indirect Buffer (IB)**. CP receives and parses the
> > > > > > Command
> > > > > > Streams (CS), and
> > > > > > -writes the operations to the correct hardware blocks.
> > > > > > +the buffer while the GPU removes operations. Finally, CP
> > > > > > is
> > > > > > also
> > > > > > responsible
> > > > > > +for handling Indirect Buffers (IB).
> > > > > > +
> > > > > > +After CP completes the first set of processing, which
> > > > > > includes
> > > > > > separate command
> > > > > > +packets specific to GFX and Compute, other blocks step in.
> > > > > > To
> > > > > > handle commands
> > > > > > +for the compute block, CPC (Command Processor Command)
> > > > > > takes
> > > > > > over,
> > > > > > and for
> > > > > > +handling Graphics operations, the CPG (Command Processor
> > > > > > Graphics)
> > > > > > takes
> > > > > > +action. Another essential block to ensure the optimal
> > > > > > utilization
> > > > > > of CPC and
> > > > > > +CPG is the CPF (Command Processor Fetcher), which helps
> > > > > > these
> > > > > > blocks to be
> > > > > > +constantly fed. Note that CPG contains the PFP (Pre-Fetch
> > > > > > Parser),
> > > > > > ME
> > > > > > +(MicroEngine), and CE (Constant Engine) in the case of
> > > > > > chips
> > > > > > that
> > > > > > support it.
> > > > > > +CPC contains MEC (MicroEngine Compute), and CPF is another
> > > > > > hardware block that
> > > > > > +provides services to CPG and CPC.
> > > > >
> > > > > I'm not sure how much value this provides to the average
> > > > > developer.
> > > > > These are sort of implementation details of the hardware. In
> > > > > general
> > > > > the driver doesn't really interact with the individual
> > > > > hardware
> > > > > blocks
> > > > > and they may not stay consistent over time.
> > > > >
> > > > > Alex
> > > >
> > > > Not sure what you mean by "the average developer", but I think
> > > > this
> > > > is
> > > > very useful knowledge to anyone who wants to contribute to
> > > > amdgpu,
> > > > specifically to the parts that have anything to do with GFX or
> > > > compute.
> > > >
> > > > If you're worried that it may not stay consistent over time, I
> > > > think
> > > > the glossary entries could be edited to mention which GPU
> > > > generation(s)
> > > > they apply to.
> > > >
> > > > As-is the code is full of 3-letter abbreviations that are never
> > > > expanded or explained anywhere, which represent various
> > > > hardware
> > > > units
> > > > (or microcontrollers, or blocks, or whatever they may be).
> > > > Without
> > > > knowing what these are and how they interact, it's difficult to
> > > > understand what the code is doing any why, or even why some
> > > > parts
> > > > are
> > > > necessary.
> > > >
> > > > To make matters worse, the latest public documentation that
> > > > tries
> > > > to
> > > > explain any of this is from 2012. So I think it's a good idea
> > > > to
> > > > collect all of this information so that newcomers to the kernel
> > > > driver
> > > > such as myself have a chance.
> > >
> > > The driver/developers don't interact with CPF, CPC, CPG directly.
> > > They just happen to be arbitrary sub-blocks of the CP. I'm
> > > concerned
> > > that adding a lot of stuff about them will just lead to
> > > confusion.
> >
> > I think they are worth a sentence or two each in the glossary.
> >
> > When trying to diagnose problems (eg. GPU hangs), we often need to
> > look
> > at various HW registers (eg. GRBM_STATUS), which refer to the above
> > sub-blocks. It is then hard to see what is going on without knowing
> > what these are. In turn, that makes it hard to come up with an
> > understanding that can explain what is happening on the HW.
> >
>
> I think that's fine. I just don't want to put too much emphasis on
> them since they are more of an implementation detail within the CP.
> They aren't quite the same as the other blocks that make up the GC
> pipeline from a driver or debugging standpoint.
I see your point.
If you want to deemphasize these, how would you feel about mentioning
them under the CP instead of giving them their own glossary entry?
>
>
> > >
> > > Documenting the micro controllers which run the firmwares makes
> > > sense
> > > as those are how the driver interacts with the CP block.
> > >
> > > CE/PFP/ME - Microcontrollers which run the firmware that provides
> > > the
> > > graphics command queues that the driver interacts with.
> > > MEC - Microcontrollers which run the firmware that provides the
> > > compute command queues that the driver interacts with.
> > > MES - Microcontrollers which run the firmware that provides the
> > > command queues that the driver uses to manage graphics and
> > > compute
> > > command queues.
> >
> > I agree and I think most (all?) of these are already in the
> > glossary.
> > If not, they should be definitely added.
> >
> > Thanks & best regards,
> > Timur
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-25 21:18 ` Timur Kristóf
@ 2025-08-26 13:21 ` Alex Deucher
2025-08-26 23:03 ` Rodrigo Siqueira
0 siblings, 1 reply; 19+ messages in thread
From: Alex Deucher @ 2025-08-26 13:21 UTC (permalink / raw)
To: Timur Kristóf
Cc: Rodrigo Siqueira, Alex Deucher, Christian König, amd-gfx,
kernel-dev
On Mon, Aug 25, 2025 at 5:18 PM Timur Kristóf <timur.kristof@gmail.com> wrote:
>
> On Mon, 2025-08-25 at 13:06 -0400, Alex Deucher wrote:
> > On Mon, Aug 25, 2025 at 12:39 PM Timur Kristóf
> > <timur.kristof@gmail.com> wrote:
> > >
> > > On Mon, 2025-08-25 at 12:31 -0400, Alex Deucher wrote:
> > > > On Mon, Aug 25, 2025 at 12:19 PM Timur Kristóf
> > > > <timur.kristof@gmail.com> wrote:
> > > > >
> > > > > On Mon, 2025-08-25 at 11:38 -0400, Alex Deucher wrote:
> > > > > > On Sun, Aug 24, 2025 at 7:43 PM Rodrigo Siqueira
> > > > > > <siqueira@igalia.com> wrote:
> > > > > >
> > > > > >
> > > > > > > +
> > > > > > > +First of all, note that the GC can have multiple SEs,
> > > > > > > depending on
> > > > > > > the specific
> > > > > > > +GPU/APU, and each SE has multiple Compute Units (CU). From
> > > > > > > the
> > > > > > > diagram, you can
> > > > > > > +see that CUs have a block named Schedulers. The reason the
> > > > > > > name is
> > > > > > > in plural is
> > > > > > > +because this hardware block is a combination of different
> > > > > > > micro-
> > > > > > > schedules: CP,
> > > > > > > +CPF, CPC, and CPG.
> > > > > >
> > > > > > CP is not really in the same category as CPF, CPC, CPG. CP
> > > > > > is
> > > > > > the
> > > > > > front end to the GC block and contains a number of micro
> > > > > > controllers
> > > > > > which run firmware which software interacts with. CPF, CPG,
> > > > > > and
> > > > > > CPC
> > > > > > are just hardware implementation details.
> > > > >
> > > > > Can you please suggest an edit that explains these better?
> > > > >
> > > > > I'm sorry to say, I thought I understood it but after reading
> > > > > your
> > > > > reply now I feel I don't.
> > > >
> > > > I would say something like:
> > > >
> > > > The CP (Command Processor) is the front end to the GC hardware.
> > > > It
> > > > provides microcontrollers which manage command queues which are
> > > > used
> > > > to feed jobs to the GFX and compute hardware.
> > >
> > > Sounds good. What do you think, Siquiera?
> > >
> > > >
> > > > >
> > > > > >
> > > > > > > +
> > > > > > > The component that acts as the front end between the CPU
> > > > > > > and
> > > > > > > the
> > > > > > > GPU is called
> > > > > > > -the Command Processor (CP). This component is responsible
> > > > > > > for
> > > > > > > providing greater
> > > > > > > +CP (Command Processor). This component is responsible for
> > > > > > > providing greater
> > > > > > > flexibility to the GC since CP makes it possible to
> > > > > > > program
> > > > > > > various aspects of
> > > > > > > the GPU pipeline. CP also coordinates the communication
> > > > > > > between
> > > > > > > the CPU and GPU
> > > > > > > via a mechanism named **Ring Buffers**, where the CPU
> > > > > > > appends
> > > > > > > information to
> > > > > > > -the buffer while the GPU removes operations. It is
> > > > > > > relevant to
> > > > > > > highlight that a
> > > > > > > -CPU can add a pointer to the Ring Buffer that points to
> > > > > > > another
> > > > > > > region of
> > > > > > > -memory outside the Ring Buffer, and CP can handle it; this
> > > > > > > mechanism is called
> > > > > > > -**Indirect Buffer (IB)**. CP receives and parses the
> > > > > > > Command
> > > > > > > Streams (CS), and
> > > > > > > -writes the operations to the correct hardware blocks.
> > > > > > > +the buffer while the GPU removes operations. Finally, CP
> > > > > > > is
> > > > > > > also
> > > > > > > responsible
> > > > > > > +for handling Indirect Buffers (IB).
> > > > > > > +
> > > > > > > +After CP completes the first set of processing, which
> > > > > > > includes
> > > > > > > separate command
> > > > > > > +packets specific to GFX and Compute, other blocks step in.
> > > > > > > To
> > > > > > > handle commands
> > > > > > > +for the compute block, CPC (Command Processor Command)
> > > > > > > takes
> > > > > > > over,
> > > > > > > and for
> > > > > > > +handling Graphics operations, the CPG (Command Processor
> > > > > > > Graphics)
> > > > > > > takes
> > > > > > > +action. Another essential block to ensure the optimal
> > > > > > > utilization
> > > > > > > of CPC and
> > > > > > > +CPG is the CPF (Command Processor Fetcher), which helps
> > > > > > > these
> > > > > > > blocks to be
> > > > > > > +constantly fed. Note that CPG contains the PFP (Pre-Fetch
> > > > > > > Parser),
> > > > > > > ME
> > > > > > > +(MicroEngine), and CE (Constant Engine) in the case of
> > > > > > > chips
> > > > > > > that
> > > > > > > support it.
> > > > > > > +CPC contains MEC (MicroEngine Compute), and CPF is another
> > > > > > > hardware block that
> > > > > > > +provides services to CPG and CPC.
> > > > > >
> > > > > > I'm not sure how much value this provides to the average
> > > > > > developer.
> > > > > > These are sort of implementation details of the hardware. In
> > > > > > general
> > > > > > the driver doesn't really interact with the individual
> > > > > > hardware
> > > > > > blocks
> > > > > > and they may not stay consistent over time.
> > > > > >
> > > > > > Alex
> > > > >
> > > > > Not sure what you mean by "the average developer", but I think
> > > > > this
> > > > > is
> > > > > very useful knowledge to anyone who wants to contribute to
> > > > > amdgpu,
> > > > > specifically to the parts that have anything to do with GFX or
> > > > > compute.
> > > > >
> > > > > If you're worried that it may not stay consistent over time, I
> > > > > think
> > > > > the glossary entries could be edited to mention which GPU
> > > > > generation(s)
> > > > > they apply to.
> > > > >
> > > > > As-is the code is full of 3-letter abbreviations that are never
> > > > > expanded or explained anywhere, which represent various
> > > > > hardware
> > > > > units
> > > > > (or microcontrollers, or blocks, or whatever they may be).
> > > > > Without
> > > > > knowing what these are and how they interact, it's difficult to
> > > > > understand what the code is doing any why, or even why some
> > > > > parts
> > > > > are
> > > > > necessary.
> > > > >
> > > > > To make matters worse, the latest public documentation that
> > > > > tries
> > > > > to
> > > > > explain any of this is from 2012. So I think it's a good idea
> > > > > to
> > > > > collect all of this information so that newcomers to the kernel
> > > > > driver
> > > > > such as myself have a chance.
> > > >
> > > > The driver/developers don't interact with CPF, CPC, CPG directly.
> > > > They just happen to be arbitrary sub-blocks of the CP. I'm
> > > > concerned
> > > > that adding a lot of stuff about them will just lead to
> > > > confusion.
> > >
> > > I think they are worth a sentence or two each in the glossary.
> > >
> > > When trying to diagnose problems (eg. GPU hangs), we often need to
> > > look
> > > at various HW registers (eg. GRBM_STATUS), which refer to the above
> > > sub-blocks. It is then hard to see what is going on without knowing
> > > what these are. In turn, that makes it hard to come up with an
> > > understanding that can explain what is happening on the HW.
> > >
> >
> > I think that's fine. I just don't want to put too much emphasis on
> > them since they are more of an implementation detail within the CP.
> > They aren't quite the same as the other blocks that make up the GC
> > pipeline from a driver or debugging standpoint.
>
> I see your point.
>
> If you want to deemphasize these, how would you feel about mentioning
> them under the CP instead of giving them their own glossary entry?
>
Sure. I think that is fine. How about something like:
For reference, internally the CP consists of several sub-blocks (CPC -
CP compute, CPG - CP graphics, and CPF - CP fetcher). Some of these
acronyms appear in register names, but this is more of an
implementation detail and not something that directly impacts driver
programming or debugging directly.
Alex
> >
> >
> > > >
> > > > Documenting the micro controllers which run the firmwares makes
> > > > sense
> > > > as those are how the driver interacts with the CP block.
> > > >
> > > > CE/PFP/ME - Microcontrollers which run the firmware that provides
> > > > the
> > > > graphics command queues that the driver interacts with.
> > > > MEC - Microcontrollers which run the firmware that provides the
> > > > compute command queues that the driver interacts with.
> > > > MES - Microcontrollers which run the firmware that provides the
> > > > command queues that the driver uses to manage graphics and
> > > > compute
> > > > command queues.
> > >
> > > I agree and I think most (all?) of these are already in the
> > > glossary.
> > > If not, they should be definitely added.
> > >
> > > Thanks & best regards,
> > > Timur
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-26 13:21 ` Alex Deucher
@ 2025-08-26 23:03 ` Rodrigo Siqueira
2025-08-27 16:56 ` Timur Kristóf
0 siblings, 1 reply; 19+ messages in thread
From: Rodrigo Siqueira @ 2025-08-26 23:03 UTC (permalink / raw)
To: Alex Deucher
Cc: Timur Kristóf, Alex Deucher, Christian König, amd-gfx,
kernel-dev
On 08/26, Alex Deucher wrote:
> On Mon, Aug 25, 2025 at 5:18 PM Timur Kristóf <timur.kristof@gmail.com> wrote:
> >
> > On Mon, 2025-08-25 at 13:06 -0400, Alex Deucher wrote:
> > > On Mon, Aug 25, 2025 at 12:39 PM Timur Kristóf
> > > <timur.kristof@gmail.com> wrote:
> > > >
> > > > On Mon, 2025-08-25 at 12:31 -0400, Alex Deucher wrote:
> > > > > On Mon, Aug 25, 2025 at 12:19 PM Timur Kristóf
> > > > > <timur.kristof@gmail.com> wrote:
> > > > > >
> > > > > > On Mon, 2025-08-25 at 11:38 -0400, Alex Deucher wrote:
> > > > > > > On Sun, Aug 24, 2025 at 7:43 PM Rodrigo Siqueira
> > > > > > > <siqueira@igalia.com> wrote:
> > > > > > >
> > > > > > >
> > > > > > > > +
> > > > > > > > +First of all, note that the GC can have multiple SEs,
> > > > > > > > depending on
> > > > > > > > the specific
> > > > > > > > +GPU/APU, and each SE has multiple Compute Units (CU). From
> > > > > > > > the
> > > > > > > > diagram, you can
> > > > > > > > +see that CUs have a block named Schedulers. The reason the
> > > > > > > > name is
> > > > > > > > in plural is
> > > > > > > > +because this hardware block is a combination of different
> > > > > > > > micro-
> > > > > > > > schedules: CP,
> > > > > > > > +CPF, CPC, and CPG.
> > > > > > >
> > > > > > > CP is not really in the same category as CPF, CPC, CPG. CP
> > > > > > > is
> > > > > > > the
> > > > > > > front end to the GC block and contains a number of micro
> > > > > > > controllers
> > > > > > > which run firmware which software interacts with. CPF, CPG,
> > > > > > > and
> > > > > > > CPC
> > > > > > > are just hardware implementation details.
> > > > > >
> > > > > > Can you please suggest an edit that explains these better?
> > > > > >
> > > > > > I'm sorry to say, I thought I understood it but after reading
> > > > > > your
> > > > > > reply now I feel I don't.
> > > > >
> > > > > I would say something like:
> > > > >
> > > > > The CP (Command Processor) is the front end to the GC hardware.
> > > > > It
> > > > > provides microcontrollers which manage command queues which are
> > > > > used
> > > > > to feed jobs to the GFX and compute hardware.
> > > >
> > > > Sounds good. What do you think, Siquiera?
> > > >
> > > > >
> > > > > >
> > > > > > >
> > > > > > > > +
> > > > > > > > The component that acts as the front end between the CPU
> > > > > > > > and
> > > > > > > > the
> > > > > > > > GPU is called
> > > > > > > > -the Command Processor (CP). This component is responsible
> > > > > > > > for
> > > > > > > > providing greater
> > > > > > > > +CP (Command Processor). This component is responsible for
> > > > > > > > providing greater
> > > > > > > > flexibility to the GC since CP makes it possible to
> > > > > > > > program
> > > > > > > > various aspects of
> > > > > > > > the GPU pipeline. CP also coordinates the communication
> > > > > > > > between
> > > > > > > > the CPU and GPU
> > > > > > > > via a mechanism named **Ring Buffers**, where the CPU
> > > > > > > > appends
> > > > > > > > information to
> > > > > > > > -the buffer while the GPU removes operations. It is
> > > > > > > > relevant to
> > > > > > > > highlight that a
> > > > > > > > -CPU can add a pointer to the Ring Buffer that points to
> > > > > > > > another
> > > > > > > > region of
> > > > > > > > -memory outside the Ring Buffer, and CP can handle it; this
> > > > > > > > mechanism is called
> > > > > > > > -**Indirect Buffer (IB)**. CP receives and parses the
> > > > > > > > Command
> > > > > > > > Streams (CS), and
> > > > > > > > -writes the operations to the correct hardware blocks.
> > > > > > > > +the buffer while the GPU removes operations. Finally, CP
> > > > > > > > is
> > > > > > > > also
> > > > > > > > responsible
> > > > > > > > +for handling Indirect Buffers (IB).
> > > > > > > > +
> > > > > > > > +After CP completes the first set of processing, which
> > > > > > > > includes
> > > > > > > > separate command
> > > > > > > > +packets specific to GFX and Compute, other blocks step in.
> > > > > > > > To
> > > > > > > > handle commands
> > > > > > > > +for the compute block, CPC (Command Processor Command)
> > > > > > > > takes
> > > > > > > > over,
> > > > > > > > and for
> > > > > > > > +handling Graphics operations, the CPG (Command Processor
> > > > > > > > Graphics)
> > > > > > > > takes
> > > > > > > > +action. Another essential block to ensure the optimal
> > > > > > > > utilization
> > > > > > > > of CPC and
> > > > > > > > +CPG is the CPF (Command Processor Fetcher), which helps
> > > > > > > > these
> > > > > > > > blocks to be
> > > > > > > > +constantly fed. Note that CPG contains the PFP (Pre-Fetch
> > > > > > > > Parser),
> > > > > > > > ME
> > > > > > > > +(MicroEngine), and CE (Constant Engine) in the case of
> > > > > > > > chips
> > > > > > > > that
> > > > > > > > support it.
> > > > > > > > +CPC contains MEC (MicroEngine Compute), and CPF is another
> > > > > > > > hardware block that
> > > > > > > > +provides services to CPG and CPC.
> > > > > > >
> > > > > > > I'm not sure how much value this provides to the average
> > > > > > > developer.
> > > > > > > These are sort of implementation details of the hardware. In
> > > > > > > general
> > > > > > > the driver doesn't really interact with the individual
> > > > > > > hardware
> > > > > > > blocks
> > > > > > > and they may not stay consistent over time.
> > > > > > >
> > > > > > > Alex
> > > > > >
> > > > > > Not sure what you mean by "the average developer", but I think
> > > > > > this
> > > > > > is
> > > > > > very useful knowledge to anyone who wants to contribute to
> > > > > > amdgpu,
> > > > > > specifically to the parts that have anything to do with GFX or
> > > > > > compute.
> > > > > >
> > > > > > If you're worried that it may not stay consistent over time, I
> > > > > > think
> > > > > > the glossary entries could be edited to mention which GPU
> > > > > > generation(s)
> > > > > > they apply to.
> > > > > >
> > > > > > As-is the code is full of 3-letter abbreviations that are never
> > > > > > expanded or explained anywhere, which represent various
> > > > > > hardware
> > > > > > units
> > > > > > (or microcontrollers, or blocks, or whatever they may be).
> > > > > > Without
> > > > > > knowing what these are and how they interact, it's difficult to
> > > > > > understand what the code is doing any why, or even why some
> > > > > > parts
> > > > > > are
> > > > > > necessary.
> > > > > >
> > > > > > To make matters worse, the latest public documentation that
> > > > > > tries
> > > > > > to
> > > > > > explain any of this is from 2012. So I think it's a good idea
> > > > > > to
> > > > > > collect all of this information so that newcomers to the kernel
> > > > > > driver
> > > > > > such as myself have a chance.
> > > > >
> > > > > The driver/developers don't interact with CPF, CPC, CPG directly.
> > > > > They just happen to be arbitrary sub-blocks of the CP. I'm
> > > > > concerned
> > > > > that adding a lot of stuff about them will just lead to
> > > > > confusion.
> > > >
> > > > I think they are worth a sentence or two each in the glossary.
> > > >
> > > > When trying to diagnose problems (eg. GPU hangs), we often need to
> > > > look
> > > > at various HW registers (eg. GRBM_STATUS), which refer to the above
> > > > sub-blocks. It is then hard to see what is going on without knowing
> > > > what these are. In turn, that makes it hard to come up with an
> > > > understanding that can explain what is happening on the HW.
> > > >
> > >
> > > I think that's fine. I just don't want to put too much emphasis on
> > > them since they are more of an implementation detail within the CP.
> > > They aren't quite the same as the other blocks that make up the GC
> > > pipeline from a driver or debugging standpoint.
> >
> > I see your point.
> >
> > If you want to deemphasize these, how would you feel about mentioning
> > them under the CP instead of giving them their own glossary entry?
> >
>
> Sure. I think that is fine. How about something like:
>
> For reference, internally the CP consists of several sub-blocks (CPC -
> CP compute, CPG - CP graphics, and CPF - CP fetcher). Some of these
> acronyms appear in register names, but this is more of an
> implementation detail and not something that directly impacts driver
> programming or debugging directly.
Hi Alex, Timur,
I attempted to incorporate all the points from the discussion into the
version of the text below. The main points are:
1. Added a link to the CU image.
1. Removed the reference to CP from the micro-schedules part.
3. Rewrite the last paragraph just to mention components like CPG, CPC,
etc.
Let me know what you think.
New version:
.. kernel-figure:: cu.svg
===> https://people.igalia.com/siqueira/kernel-doc-imgs/cu.svg
First of all, note that the GC can have multiple SEs, depending on the specific
GPU/APU, and each SE has multiple Compute Units (CU). From the diagram, you can
see that CUs have a block named Schedulers. The reason the name is in plural is
because this hardware block is a combination of different micro-schedules: CPF,
CPC, and CPG.
The component that acts as the front end between the CPU and the GPU is called
CP (Command Processor). This component is responsible for providing greater
flexibility to the GC since CP makes it possible to program various aspects of
the GPU pipeline. CP also coordinates the communication between the CPU and GPU
via a mechanism named **Ring Buffers**, where the CPU appends information to
the buffer while the GPU removes operations. Finally, CP is also responsible
for handling Indirect Buffers (IB).
After CP completes the first set of processing, which includes separate command
packets specific to GFX and Compute, other blocks step in. For reference,
internally the CP consists of several sub-blocks (CPC - CP compute, CPG - CP
graphics, and CPF - CP fetcher). Some of these acronyms appear in register
names, but this is more of an implementation detail and not something that
directly impacts driver programming or debugging directly.
Thanks
>
> Alex
>
>
> > >
> > >
> > > > >
> > > > > Documenting the micro controllers which run the firmwares makes
> > > > > sense
> > > > > as those are how the driver interacts with the CP block.
> > > > >
> > > > > CE/PFP/ME - Microcontrollers which run the firmware that provides
> > > > > the
> > > > > graphics command queues that the driver interacts with.
> > > > > MEC - Microcontrollers which run the firmware that provides the
> > > > > compute command queues that the driver interacts with.
> > > > > MES - Microcontrollers which run the firmware that provides the
> > > > > command queues that the driver uses to manage graphics and
> > > > > compute
> > > > > command queues.
> > > >
> > > > I agree and I think most (all?) of these are already in the
> > > > glossary.
> > > > If not, they should be definitely added.
> > > >
> > > > Thanks & best regards,
> > > > Timur
--
Rodrigo Siqueira
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 5/5] Documentation/gpu: Add documentation about ring buffer
2025-08-25 15:58 ` Alex Deucher
@ 2025-08-26 23:53 ` Rodrigo Siqueira
0 siblings, 0 replies; 19+ messages in thread
From: Rodrigo Siqueira @ 2025-08-26 23:53 UTC (permalink / raw)
To: Alex Deucher
Cc: Alex Deucher, Christian König, Timur Kristóf, amd-gfx,
kernel-dev
On 08/25, Alex Deucher wrote:
> On Sun, Aug 24, 2025 at 7:58 PM Rodrigo Siqueira <siqueira@igalia.com> wrote:
> >
> > AMDGPU heavily relies on ring buffers to manage its components; as a
> > result, it has an elaborate mechanism of operation with multiple details
> > around it. This commit introduces new documentation on ring buffers,
> > detailing their management and expanding the explanation of Enforce
> > isolation. Finally, this commit also adds the documentation available in
> > the amdgpu_ring.c file to it.
> >
> > Cc: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Christian König <christian.koenig@amd.com>
> > Cc: Timur Kristóf <timur.kristof@gmail.com>
> > Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
> > ---
> > .../gpu/amdgpu/enforce_isolation.svg | 707 +++++++
> > Documentation/gpu/amdgpu/gfx_pipeline_seq.svg | 413 +++++
> > Documentation/gpu/amdgpu/index.rst | 1 +
> > .../gpu/amdgpu/no_enforce_isolation.svg | 673 +++++++
> > Documentation/gpu/amdgpu/ring-buffer.rst | 94 +
> > Documentation/gpu/amdgpu/ring_buffers.svg | 1633 +++++++++++++++++
> > 6 files changed, 3521 insertions(+)
> > create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
> > create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
> > create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
> > create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
> > create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg
> >
>
> Do you have links to the images?
Hi,
For reference, I'll add all links here, but you can also view them in
the comments you've made below for a better context.
https://people.igalia.com/siqueira/kernel-doc-imgs/enforce_isolation.svg
https://people.igalia.com/siqueira/kernel-doc-imgs/gfx_pipeline_seq.svg
https://people.igalia.com/siqueira/kernel-doc-imgs/no_enforce_isolation.svg
https://people.igalia.com/siqueira/kernel-doc-imgs/ring_buffers.svg
>
> > diff --git a/Documentation/gpu/amdgpu/enforce_isolation.svg b/Documentation/gpu/amdgpu/enforce_isolation.svg
> > new file mode 100644
> > index 000000000000..b224615e1611
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/enforce_isolation.svg
> > @@ -0,0 +1,707 @@
> > +<?xml version="1.0" encoding="UTF-8" standalone="no"?>
> > +<!-- Created with Inkscape (http://www.inkscape.org/) -->
> > +
> > +<svg
> > + width="68.949203mm"
> > + height="86.909332mm"
> > + viewBox="0 0 68.949202 86.909332"
> > + version="1.1"
> > + id="svg1"
> > + inkscape:version="1.4 (e7c3feb100, 2024-10-09)"
> > + sodipodi:docname="enforce_isolation.svg"
> > + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
> > + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
> > + xmlns="http://www.w3.org/2000/svg"
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> > diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
> > index bb2894b5edaf..1f0e8a38c625 100644
> > --- a/Documentation/gpu/amdgpu/index.rst
> > +++ b/Documentation/gpu/amdgpu/index.rst
> > @@ -8,6 +8,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
> > .. toctree::
> >
> > driver-core
> > + ring-buffer
> > amd-hardware-list-info
> > module-parameters
> > gc/index
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> > + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:2.60421px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle;fill:#1c241c;stroke-width:0.134424"
> > + id="tspan4">into the ring</tspan></text>
> > + </g>
> > + </g>
> > +</svg>
> > diff --git a/Documentation/gpu/amdgpu/ring-buffer.rst b/Documentation/gpu/amdgpu/ring-buffer.rst
> > new file mode 100644
> > index 000000000000..40c189c9dab4
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/ring-buffer.rst
> > @@ -0,0 +1,94 @@
> > +=============
> > + Ring Buffer
> > +=============
> > +
> > +To handle communication between user space and kernel space, amdgpu adopts a
> > +strategy based on a ring buffer, which is used by GFX, Compute, SDMA, UVD, VCE,
> > +VCN, VPE, KIQ, MES, UMSCH, and CPER. See the figure below that illustrates how
> > +this communication works:
> > +
> > +.. kernel-figure:: ring_buffers.svg
https://people.igalia.com/siqueira/kernel-doc-imgs/ring_buffers.svg
> > +
> > +Ring buffers in the amdgpu work as a producer-consumer problem, where userspace
> > +acts as the producer, constantly filling the ring buffer with GPU commands to
> > +be executed. Meanwhile, the GPU retrieves the information from the ring, parses
> > +it, and distributes the specific set of instructions between the different
> > +amdgpu blocks. Notice from the diagram that the ring has a Read Pointer (rptr)
> > +that indicates where the GPU is currently reading, and there is a Write Pointer
> > +(wptr) that indicates where the host has written the message. Note that every
> > +time something is written to the ring, the wptr is incremented. Meanwhile, the
> > +GPU constantly updates the rptr pointer, chasing the wptr until both pointers
> > +are equal. The user space or the driver can utilize the rptr pointer to roughly
>
> User space or the driver
>
> > +estimate how many instructions are still pending completion (keep in mind that
> > +rptr might not be precise).
>
> You might want to drop the comment in the paranthesis. If you read
> back the actual
> rptr register, it should be correct, but the driver generally uses a
> rptr shadow in memory which the engine may only update periodically.
>
> > +
> > +Usually, ring buffers in the driver have a limited size (search for occurrences
> > +of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is
> > +that CP (Command Processor) is capable of following addresses inserted into the
> > +ring; this is illustrated in the image by the reference to the IB (Indirect
> > +Buffer). The IB gives userspace the possibility to have an area in memory that
> > +CP can read and feed the hardware with extra instructions.
> > +
> > +Enforce Isolation
> > +=================
> > +
> > +Before examining the Enforce Isolation mechanism in the ring buffer context, it
> > +is important to discuss two concepts: where the ring buffer is located and how
> > +instructions from the ring buffer are processed in the graphics pipeline.
> > +
> > +All ASICs pre-GFX11 use what is called a kernel queue, which means the ring is
>
> gfx11 and 12 still use kernel queues, they just happen to also support
> user queues.
Is it enough if I change the next phrase to:
GFX11 and newer support kernel [..]
>
> > +allocated in kernel space and has some restrictions, such as not being able to
> > +map and unmap queues after initialization. GFX12 and newer support kernel
>
> Kernel queues can be mapped an unmapped, the scheduler just never preempts them.
What do you think about this rerwirte:
All ASICs pre-GFX11 use what is called a kernel queue, which means the
ring is allocated in kernel space, and they can also be mapped and
unmapped. One restriction that kernel queues have is that the scheduler
never preempts them.
>
> > +queues, but also provide a new mechanism named user queues, where the queue is
> > +moved to the user space and can be mapped and unmapped. In practical terms, the
> > +kernel queue approach inserts all GPU commands created by userspace into the
> > +same set of rings, albeit in a mixed manner. See the picture below illustrating
> > +this scenario:
> > +
> > +.. kernel-figure:: no_enforce_isolation.svg
> > +
> > +Note from the diagram that there is no guarantee of order or a clear separation
> > +between instructions, which is not a problem most of the time, and this is also
>
> I haven't looked at the images yet, but the jobs are added
> sequentially, it's just that because the GC engine is pipelined, you
> can have multiple things overlapping.
Here is the image:
https://people.igalia.com/siqueira/kernel-doc-imgs/no_enforce_isolation.svg
Could you elaborate more about "it's just that because the GC engine is
pipelined"?
>
> > +good for performance. In terms of executing those instructions in the GFX, it
> > +must follow a pipeline that usually follows the following sequence: Shader
> > +Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan
> > +Converter (SC), Primitive Assembler (PA), and cache manipulation (this may
> > +change between ASICs). Another common way to describe the pipeline is to use
> > +Pixel Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader
> > +stages. The diagram below illustrates the sequence described in the paragraph.
>
> I think the rest of this paragraph is unrelated to enforce isolation.
> I think it should be moved somewhere else to describe the hardware
> pipeline.
I added it here to aid comprehension of the topics discussed in the next
paragraph. If you want, I can create a new page under the "gc" folder
named "hardware pipeline", I just don't know what else to add there.
>
> > +
> > +.. kernel-figure:: gfx_pipeline_seq.svg
https://people.igalia.com/siqueira/kernel-doc-imgs/gfx_pipeline_seq.svg
> > +
> > +The use of the kernel queue is the default behaviour in amdgpu pre-GFX11 and in
> > +many cases in newer ASICs. Although this solution is considered stable and
> > +performs well, it also creates some intricate issues when something goes wrong.
> > +The problem with this solution is that pinpointing which job caused an issue
> > +can be challenging in some situations, which can complicate the debugging in
> > +circumstances where the GPU recovery was triggered. For instance, if Job A
> > +causes a hang issue, Job B's instruction might already be executing, and we
> > +could incorrectly identify Job B as the problematic one. To mitigate this
> > +problem, it was introduced the concept of Enforce Isolation that can be seen in
> > +the below picture:
> > +
> > +.. kernel-figure:: enforce_isolation.svg
> > +
> > +As shown in the diagram, enforcing isolation introduces a level of ordering
> > +between submissions, since the access to GFX/Compute is serialized. Notice that
> > +this approach has a minimal performance impact, as it only allows one job to
> > +submit commands at a time. However, this is not a notable problem, and the
> > +benefit of better pinpointing the job that caused a problem outweighs the
> > +performance impact. Although enforcing isolation improves the situation, it
> > +does not fully resolve the issue of pinpointing bad jobs, as we can still
> > +encounter scenarios where Job A hangs while Job B is running, leading to the
> > +wrong blame of Job B. To avoid this issue, an additional element is introduced
> > +to enforce isolation, as represented by the circles in the diagram. Every
> > +circle is a wait for cache flushing, which ensures that when the next job
> > +starts, it starts in a clean state, and if some issues happen, we can point to
> > +the bad process more precisely.
>
> I haven't seen the diagram yet, but this doesn't sound completely
> correct. The driver inserts a fence wait between jobs in each ring to
> make sure there is no overlapping work in the ring itself. However,
> that is independent of enforce isolation. If you enable enforce
> isolation, all jobs going to all GC queues are serialized.
Here is the image:
https://people.igalia.com/siqueira/kernel-doc-imgs/enforce_isolation.svg
So... what I described in the image is just the expected behavior?
Thanks
Siqueira
>
> Alex
>
> > +
> > +Ring Operations
> > +===============
> > +
> > +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > + :internal:
> > +
> > diff --git a/Documentation/gpu/amdgpu/ring_buffers.svg b/Documentation/gpu/amdgpu/ring_buffers.svg
> > new file mode 100644
> > index 000000000000..7a6fcb19e151
> > --- /dev/null
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> > --
> > 2.47.2
> >
--
Rodrigo Siqueira
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v2 4/5] Documentation/gpu: Add more information about GC
2025-08-26 23:03 ` Rodrigo Siqueira
@ 2025-08-27 16:56 ` Timur Kristóf
0 siblings, 0 replies; 19+ messages in thread
From: Timur Kristóf @ 2025-08-27 16:56 UTC (permalink / raw)
To: Rodrigo Siqueira, Alex Deucher
Cc: Alex Deucher, Christian König, amd-gfx, kernel-dev
On Tue, 2025-08-26 at 17:03 -0600, Rodrigo Siqueira wrote:
> On 08/26, Alex Deucher wrote:
> > On Mon, Aug 25, 2025 at 5:18 PM Timur Kristóf
> > <timur.kristof@gmail.com> wrote:
> > >
> > > On Mon, 2025-08-25 at 13:06 -0400, Alex Deucher wrote:
> > > > On Mon, Aug 25, 2025 at 12:39 PM Timur Kristóf
> > > > <timur.kristof@gmail.com> wrote:
> > > > >
> > > > > On Mon, 2025-08-25 at 12:31 -0400, Alex Deucher wrote:
> > > > > > On Mon, Aug 25, 2025 at 12:19 PM Timur Kristóf
> > > > > > <timur.kristof@gmail.com> wrote:
> > > > > > >
> > > > > > > On Mon, 2025-08-25 at 11:38 -0400, Alex Deucher wrote:
> > > > > > > > On Sun, Aug 24, 2025 at 7:43 PM Rodrigo Siqueira
> > > > > > > > <siqueira@igalia.com> wrote:
> > > > > > > >
> > > > > > > >
> > > > > > > > > +
> > > > > > > > > +First of all, note that the GC can have multiple
> > > > > > > > > SEs,
> > > > > > > > > depending on
> > > > > > > > > the specific
> > > > > > > > > +GPU/APU, and each SE has multiple Compute Units
> > > > > > > > > (CU). From
> > > > > > > > > the
> > > > > > > > > diagram, you can
> > > > > > > > > +see that CUs have a block named Schedulers. The
> > > > > > > > > reason the
> > > > > > > > > name is
> > > > > > > > > in plural is
> > > > > > > > > +because this hardware block is a combination of
> > > > > > > > > different
> > > > > > > > > micro-
> > > > > > > > > schedules: CP,
> > > > > > > > > +CPF, CPC, and CPG.
> > > > > > > >
> > > > > > > > CP is not really in the same category as CPF, CPC,
> > > > > > > > CPG. CP
> > > > > > > > is
> > > > > > > > the
> > > > > > > > front end to the GC block and contains a number of
> > > > > > > > micro
> > > > > > > > controllers
> > > > > > > > which run firmware which software interacts with. CPF,
> > > > > > > > CPG,
> > > > > > > > and
> > > > > > > > CPC
> > > > > > > > are just hardware implementation details.
> > > > > > >
> > > > > > > Can you please suggest an edit that explains these
> > > > > > > better?
> > > > > > >
> > > > > > > I'm sorry to say, I thought I understood it but after
> > > > > > > reading
> > > > > > > your
> > > > > > > reply now I feel I don't.
> > > > > >
> > > > > > I would say something like:
> > > > > >
> > > > > > The CP (Command Processor) is the front end to the GC
> > > > > > hardware.
> > > > > > It
> > > > > > provides microcontrollers which manage command queues which
> > > > > > are
> > > > > > used
> > > > > > to feed jobs to the GFX and compute hardware.
> > > > >
> > > > > Sounds good. What do you think, Siquiera?
> > > > >
> > > > > >
> > > > > > >
> > > > > > > >
> > > > > > > > > +
> > > > > > > > > The component that acts as the front end between the
> > > > > > > > > CPU
> > > > > > > > > and
> > > > > > > > > the
> > > > > > > > > GPU is called
> > > > > > > > > -the Command Processor (CP). This component is
> > > > > > > > > responsible
> > > > > > > > > for
> > > > > > > > > providing greater
> > > > > > > > > +CP (Command Processor). This component is
> > > > > > > > > responsible for
> > > > > > > > > providing greater
> > > > > > > > > flexibility to the GC since CP makes it possible to
> > > > > > > > > program
> > > > > > > > > various aspects of
> > > > > > > > > the GPU pipeline. CP also coordinates the
> > > > > > > > > communication
> > > > > > > > > between
> > > > > > > > > the CPU and GPU
> > > > > > > > > via a mechanism named **Ring Buffers**, where the
> > > > > > > > > CPU
> > > > > > > > > appends
> > > > > > > > > information to
> > > > > > > > > -the buffer while the GPU removes operations. It is
> > > > > > > > > relevant to
> > > > > > > > > highlight that a
> > > > > > > > > -CPU can add a pointer to the Ring Buffer that points
> > > > > > > > > to
> > > > > > > > > another
> > > > > > > > > region of
> > > > > > > > > -memory outside the Ring Buffer, and CP can handle
> > > > > > > > > it; this
> > > > > > > > > mechanism is called
> > > > > > > > > -**Indirect Buffer (IB)**. CP receives and parses the
> > > > > > > > > Command
> > > > > > > > > Streams (CS), and
> > > > > > > > > -writes the operations to the correct hardware
> > > > > > > > > blocks.
> > > > > > > > > +the buffer while the GPU removes operations.
> > > > > > > > > Finally, CP
> > > > > > > > > is
> > > > > > > > > also
> > > > > > > > > responsible
> > > > > > > > > +for handling Indirect Buffers (IB).
> > > > > > > > > +
> > > > > > > > > +After CP completes the first set of processing,
> > > > > > > > > which
> > > > > > > > > includes
> > > > > > > > > separate command
> > > > > > > > > +packets specific to GFX and Compute, other blocks
> > > > > > > > > step in.
> > > > > > > > > To
> > > > > > > > > handle commands
> > > > > > > > > +for the compute block, CPC (Command Processor
> > > > > > > > > Command)
> > > > > > > > > takes
> > > > > > > > > over,
> > > > > > > > > and for
> > > > > > > > > +handling Graphics operations, the CPG (Command
> > > > > > > > > Processor
> > > > > > > > > Graphics)
> > > > > > > > > takes
> > > > > > > > > +action. Another essential block to ensure the
> > > > > > > > > optimal
> > > > > > > > > utilization
> > > > > > > > > of CPC and
> > > > > > > > > +CPG is the CPF (Command Processor Fetcher), which
> > > > > > > > > helps
> > > > > > > > > these
> > > > > > > > > blocks to be
> > > > > > > > > +constantly fed. Note that CPG contains the PFP (Pre-
> > > > > > > > > Fetch
> > > > > > > > > Parser),
> > > > > > > > > ME
> > > > > > > > > +(MicroEngine), and CE (Constant Engine) in the case
> > > > > > > > > of
> > > > > > > > > chips
> > > > > > > > > that
> > > > > > > > > support it.
> > > > > > > > > +CPC contains MEC (MicroEngine Compute), and CPF is
> > > > > > > > > another
> > > > > > > > > hardware block that
> > > > > > > > > +provides services to CPG and CPC.
> > > > > > > >
> > > > > > > > I'm not sure how much value this provides to the
> > > > > > > > average
> > > > > > > > developer.
> > > > > > > > These are sort of implementation details of the
> > > > > > > > hardware. In
> > > > > > > > general
> > > > > > > > the driver doesn't really interact with the individual
> > > > > > > > hardware
> > > > > > > > blocks
> > > > > > > > and they may not stay consistent over time.
> > > > > > > >
> > > > > > > > Alex
> > > > > > >
> > > > > > > Not sure what you mean by "the average developer", but I
> > > > > > > think
> > > > > > > this
> > > > > > > is
> > > > > > > very useful knowledge to anyone who wants to contribute
> > > > > > > to
> > > > > > > amdgpu,
> > > > > > > specifically to the parts that have anything to do with
> > > > > > > GFX or
> > > > > > > compute.
> > > > > > >
> > > > > > > If you're worried that it may not stay consistent over
> > > > > > > time, I
> > > > > > > think
> > > > > > > the glossary entries could be edited to mention which GPU
> > > > > > > generation(s)
> > > > > > > they apply to.
> > > > > > >
> > > > > > > As-is the code is full of 3-letter abbreviations that are
> > > > > > > never
> > > > > > > expanded or explained anywhere, which represent various
> > > > > > > hardware
> > > > > > > units
> > > > > > > (or microcontrollers, or blocks, or whatever they may
> > > > > > > be).
> > > > > > > Without
> > > > > > > knowing what these are and how they interact, it's
> > > > > > > difficult to
> > > > > > > understand what the code is doing any why, or even why
> > > > > > > some
> > > > > > > parts
> > > > > > > are
> > > > > > > necessary.
> > > > > > >
> > > > > > > To make matters worse, the latest public documentation
> > > > > > > that
> > > > > > > tries
> > > > > > > to
> > > > > > > explain any of this is from 2012. So I think it's a good
> > > > > > > idea
> > > > > > > to
> > > > > > > collect all of this information so that newcomers to the
> > > > > > > kernel
> > > > > > > driver
> > > > > > > such as myself have a chance.
> > > > > >
> > > > > > The driver/developers don't interact with CPF, CPC, CPG
> > > > > > directly.
> > > > > > They just happen to be arbitrary sub-blocks of the CP. I'm
> > > > > > concerned
> > > > > > that adding a lot of stuff about them will just lead to
> > > > > > confusion.
> > > > >
> > > > > I think they are worth a sentence or two each in the
> > > > > glossary.
> > > > >
> > > > > When trying to diagnose problems (eg. GPU hangs), we often
> > > > > need to
> > > > > look
> > > > > at various HW registers (eg. GRBM_STATUS), which refer to the
> > > > > above
> > > > > sub-blocks. It is then hard to see what is going on without
> > > > > knowing
> > > > > what these are. In turn, that makes it hard to come up with
> > > > > an
> > > > > understanding that can explain what is happening on the HW.
> > > > >
> > > >
> > > > I think that's fine. I just don't want to put too much
> > > > emphasis on
> > > > them since they are more of an implementation detail within the
> > > > CP.
> > > > They aren't quite the same as the other blocks that make up the
> > > > GC
> > > > pipeline from a driver or debugging standpoint.
> > >
> > > I see your point.
> > >
> > > If you want to deemphasize these, how would you feel about
> > > mentioning
> > > them under the CP instead of giving them their own glossary
> > > entry?
> > >
> >
> > Sure. I think that is fine. How about something like:
> >
> > For reference, internally the CP consists of several sub-blocks
> > (CPC -
> > CP compute, CPG - CP graphics, and CPF - CP fetcher). Some of
> > these
> > acronyms appear in register names, but this is more of an
> > implementation detail and not something that directly impacts
> > driver
> > programming or debugging directly.
>
>
> Hi Alex, Timur,
>
> I attempted to incorporate all the points from the discussion into
> the
> version of the text below. The main points are:
>
> 1. Added a link to the CU image.
> 1. Removed the reference to CP from the micro-schedules part.
> 3. Rewrite the last paragraph just to mention components like CPG,
> CPC,
> etc.
>
> Let me know what you think.
>
> New version:
>
> .. kernel-figure:: cu.svg
> ===> https://people.igalia.com/siqueira/kernel-doc-imgs/cu.svg
>
I think this is mixed up and doesn't look right to me.
First, WGP (workgroup processor) is only relevant on GFX10+ (that is,
Navi 10 or newer). CU (compute unit) is something that all GCN and RDNA
GPUs have. These are already well documented publicly, and I don't
think we need another diagram for them.
For reference, you can find a diagram of a GCN CU on page 5 here:
https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/vega-7nm-shader-instruction-set-architecture.pdf
And a diagram of an RDNA WGP on page 6 here:
https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna4-instruction-set-architecture.pdf
The above diagrams do mention commands processors although not in
detail. As you can see, the command processors are not part of a CU.
Rather, they can generate work for the various CUs/WGPs.
As far as I understand, there is only one of each CP per queue (or per
pipe, I am somewhat mixed up myself about the differences between a
queue and a pipe). For example, each compute queue has its own MEC, and
any MEC can launch work on any CU.
Please correct me if I'm wrong about it.
Timur
> First of all, note that the GC can have multiple SEs, depending on
> the specific
> GPU/APU, and each SE has multiple Compute Units (CU). From the
> diagram, you can
> see that CUs have a block named Schedulers. The reason the name is in
> plural is
> because this hardware block is a combination of different micro-
> schedules: CPF,
> CPC, and CPG.
>
> The component that acts as the front end between the CPU and the GPU
> is called
> CP (Command Processor). This component is responsible for providing
> greater
> flexibility to the GC since CP makes it possible to program various
> aspects of
> the GPU pipeline. CP also coordinates the communication between the
> CPU and GPU
> via a mechanism named **Ring Buffers**, where the CPU appends
> information to
> the buffer while the GPU removes operations. Finally, CP is also
> responsible
> for handling Indirect Buffers (IB).
>
> After CP completes the first set of processing, which includes
> separate command
> packets specific to GFX and Compute, other blocks step in. For
> reference,
> internally the CP consists of several sub-blocks (CPC - CP compute,
> CPG - CP
> graphics, and CPF - CP fetcher). Some of these acronyms appear in
> register
> names, but this is more of an implementation detail and not something
> that
> directly impacts driver programming or debugging directly.
>
> Thanks
>
> >
> > Alex
> >
> >
> > > >
> > > >
> > > > > >
> > > > > > Documenting the micro controllers which run the firmwares
> > > > > > makes
> > > > > > sense
> > > > > > as those are how the driver interacts with the CP block.
> > > > > >
> > > > > > CE/PFP/ME - Microcontrollers which run the firmware that
> > > > > > provides
> > > > > > the
> > > > > > graphics command queues that the driver interacts with.
> > > > > > MEC - Microcontrollers which run the firmware that provides
> > > > > > the
> > > > > > compute command queues that the driver interacts with.
> > > > > > MES - Microcontrollers which run the firmware that provides
> > > > > > the
> > > > > > command queues that the driver uses to manage graphics and
> > > > > > compute
> > > > > > command queues.
> > > > >
> > > > > I agree and I think most (all?) of these are already in the
> > > > > glossary.
> > > > > If not, they should be definitely added.
> > > > >
> > > > > Thanks & best regards,
> > > > > Timur
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2025-08-27 16:56 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-24 23:29 [PATCH v2 0/5] Expand kernel-doc with more generic details and info about ring buffers Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 1/5] drm/amdgpu: Expand kernel-doc in amdgpu_ring Rodrigo Siqueira
2025-08-25 15:19 ` Christian König
2025-08-25 16:04 ` Timur Kristóf
2025-08-24 23:29 ` [PATCH v2 2/5] Documentation/gpu: Add new glossary entries from UMR Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 3/5] Documentation/gpu: Expand generic block information Rodrigo Siqueira
2025-08-24 23:29 ` [PATCH v2 4/5] Documentation/gpu: Add more information about GC Rodrigo Siqueira
2025-08-25 15:38 ` Alex Deucher
2025-08-25 16:19 ` Timur Kristóf
2025-08-25 16:31 ` Alex Deucher
2025-08-25 16:39 ` Timur Kristóf
2025-08-25 17:06 ` Alex Deucher
2025-08-25 21:18 ` Timur Kristóf
2025-08-26 13:21 ` Alex Deucher
2025-08-26 23:03 ` Rodrigo Siqueira
2025-08-27 16:56 ` Timur Kristóf
2025-08-24 23:29 ` [PATCH v2 5/5] Documentation/gpu: Add documentation about ring buffer Rodrigo Siqueira
2025-08-25 15:58 ` Alex Deucher
2025-08-26 23:53 ` Rodrigo Siqueira
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