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From: "Christian König" <christian.koenig@amd.com>
To: "Christian König" <ckoenig.leichtzumerken@gmail.com>,
	luben.tuikov@amd.com, dri-devel@lists.freedesktop.org,
	amd-gfx@lists.freedesktop.org,
	"Alex Deucher" <Alexander.Deucher@amd.com>
Subject: Re: [PATCH 1/2] drm/sched: add DRM_SCHED_FENCE_DONT_PIPELINE flag
Date: Tue, 18 Oct 2022 17:11:04 +0200	[thread overview]
Message-ID: <c8585fab-6e8d-de4b-eb2a-e8bff6e3fde8@amd.com> (raw)
In-Reply-To: <20221014081553.114899-1-christian.koenig@amd.com>

Gentle ping to others to get this reviewed.

Alex, this is fixing the TLB flush errors and I think we need to get it 
into -fixes ASAP.

Christian.

Am 14.10.22 um 10:15 schrieb Christian König:
> Setting this flag on a scheduler fence prevents pipelining of jobs
> depending on this fence. In other words we always insert a full CPU
> round trip before dependen jobs are pushed to the pipeline.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> CC: stable@vger.kernel.org # 5.19+
> ---
>   drivers/gpu/drm/scheduler/sched_entity.c | 3 ++-
>   include/drm/gpu_scheduler.h              | 9 +++++++++
>   2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c
> index 191c56064f19..43d337d8b153 100644
> --- a/drivers/gpu/drm/scheduler/sched_entity.c
> +++ b/drivers/gpu/drm/scheduler/sched_entity.c
> @@ -385,7 +385,8 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity)
>   	}
>   
>   	s_fence = to_drm_sched_fence(fence);
> -	if (s_fence && s_fence->sched == sched) {
> +	if (s_fence && s_fence->sched == sched &&
> +	    !test_bit(DRM_SCHED_FENCE_DONT_PIPELINE, &fence->flags)) {
>   
>   		/*
>   		 * Fence is from the same scheduler, only need to wait for
> diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
> index 0fca8f38bee4..f01d14b231ed 100644
> --- a/include/drm/gpu_scheduler.h
> +++ b/include/drm/gpu_scheduler.h
> @@ -32,6 +32,15 @@
>   
>   #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000)
>   
> +/**
> + * DRM_SCHED_FENCE_DONT_PIPELINE - Prefent dependency pipelining
> + *
> + * Setting this flag on a scheduler fence prevents pipelining of jobs depending
> + * on this fence. In other words we always insert a full CPU round trip before
> + * dependen jobs are pushed to the hw queue.
> + */
> +#define DRM_SCHED_FENCE_DONT_PIPELINE	DMA_FENCE_FLAG_USER_BITS
> +
>   struct drm_gem_object;
>   
>   struct drm_gpu_scheduler;


  parent reply	other threads:[~2022-10-18 15:11 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-14  8:15 [PATCH 1/2] drm/sched: add DRM_SCHED_FENCE_DONT_PIPELINE flag Christian König
2022-10-14  8:15 ` [PATCH 2/2] drm/amdgpu: use DRM_SCHED_FENCE_DONT_PIPELINE for VM updates Christian König
2022-10-17  5:29   ` Luben Tuikov
2022-10-17  6:27     ` Christian König
2022-10-24  7:20       ` Luben Tuikov
2022-10-18 15:11 ` Christian König [this message]
2022-10-18 15:37   ` [PATCH 1/2] drm/sched: add DRM_SCHED_FENCE_DONT_PIPELINE flag Alex Deucher
2022-10-18 22:24     ` Luben Tuikov
2022-10-24  7:17 ` Luben Tuikov

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