Re: [PATCH 1/3] drm/ttm: add set_pages_wb for handling page order more than zero

["Christian König" <ckoenig.leichtzumerken@gmail.com>]

Am 22.11.2017 um 12:50 schrieb Chris Wilson:
> Quoting Roger He (2017-11-22 11:44:27)
>> Change-Id: Idf5ccb579d264b343199d8b8344bddeec2c0019f
>> Signed-off-by: Roger He <Hongbo.He@amd.com>
>> ---
>>   drivers/gpu/drm/ttm/ttm_page_alloc.c | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
>> index a8b2bfa..cdbb731 100644
>> --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
>> +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
>> @@ -223,6 +223,17 @@ static struct kobj_type ttm_pool_kobj_type = {
>>   static struct ttm_pool_manager *_manager;
>>   
>>   #ifndef CONFIG_X86
>> +static int set_pages_wb(struct page *page, int numpages)
>> +{
>> +#if IS_ENABLED(CONFIG_AGP)
>> +       int i;
>> +
>> +       for (i = 0; i < numpages; i++)
>> +               unmap_page_from_agp(page++);
>> +#endif
>> +       return 0;
>> +}
>> +
>>   static int set_pages_array_wb(struct page **pages, int addrinarray)
> Both of these are shadowing exports from arch/x86, probably not the
> wisest choice of names.

That is intended, please note the "#ifndef CONFIG_X86".

Basically TTM provides the same function for other architectures that we 
have for X86.

Christian.

> -Chris
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