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[165.204.72.6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3680dab3e71sm6710245f8f.12.2024.07.15.08.30.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Jul 2024 08:30:28 -0700 (PDT) Message-ID: Date: Mon, 15 Jul 2024 17:30:26 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] drm/amdgpu: Add empty HDP flush function to JPEG v4.0.3 To: "Lazar, Lijo" , Jane Jian , Haijun.Chang@amd.com, Victor.Zhao@amd.com Cc: amd-gfx@lists.freedesktop.org References: <20240715144748.168556-1-Jane.Jian@amd.com> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Am 15.07.24 um 17:08 schrieb Lazar, Lijo: > > On 7/15/2024 8:28 PM, Christian König wrote: >> >> Am 15.07.24 um 16:47 schrieb Jane Jian: >>> From: Lijo Lazar >>> >>> JPEG v4.0.3 doesn't support HDP flush when RRMT is enabled. Instead, >>> mmsch fw will do the flush. >>> >>> Signed-off-by: Lijo Lazar >>> Signed-off-by: Jane Jian >>> --- >>>   drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 9 +++++++++ >>>   1 file changed, 9 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c >>> b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c >>> index 04d8966423de..ea601047dab0 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c >>> @@ -621,6 +621,14 @@ static uint64_t >>> jpeg_v4_0_3_dec_ring_get_wptr(struct amdgpu_ring *ring) >>>               ring->pipe ? (0x40 * ring->pipe - 0xc80) : 0); >>>   } >>>   +static void jpeg_v4_0_3_ring_emit_hdp_flush(struct amdgpu_ring *ring) >>> +{ >>> +    /* VCN engine access for HDP flush doesn't work when RRMT is >>> enabled. >>> +     * This is a workaround to avoid any HDP flush through VCN ring. >>> Instead >>> +     * HDP flush will be done by driver while submitting doorbell. >> I think that should read "HDP flush will be done by firmware ....". >> >> Or is it really the driver which should do this? In this case the patch >> here would be wrong. >> > That's a copy-paste mistake. This comment was originally in the initial > version of the patch. Yeah thought so. > Discussed with Jane and she'll be sending a revised version. Also, there > is a third patch expected which does normalization of register offsets > when submitted through ring. Another question is if we have ever released JPEG/VCN firmware which doesn't do the flush? If yes then we need a version check here to provide backward compatibility with already released firmware. Regards, Christian. > > Thanks, > Lijo > >> Regards, >> Christian. >> >>> +     */ >>> +} >>> + >>>   /** >>>    * jpeg_v4_0_3_dec_ring_set_wptr - set write pointer >>>    * >>> @@ -1072,6 +1080,7 @@ static const struct amdgpu_ring_funcs >>> jpeg_v4_0_3_dec_ring_vm_funcs = { >>>       .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, >>>       .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence, >>>       .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush, >>> +    .emit_hdp_flush = jpeg_v4_0_3_ring_emit_hdp_flush, >>>       .test_ring = amdgpu_jpeg_dec_ring_test_ring, >>>       .test_ib = amdgpu_jpeg_dec_ring_test_ib, >>>       .insert_nop = jpeg_v4_0_3_dec_ring_nop,